From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57328314B97; Wed, 15 Oct 2025 06:46:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760510806; cv=none; b=eryINLFXcb3iPj64BlpXTZV1iGCKiEe1X6YFBXChV+NjiIexmcvVS5eyGC9O7n/B5Tj/vhT7pWLKmgY7DB3sqvhdKmZFSKacqbuDunEYu/Rz45FF1Wu8gKpC9KbbRt2Qkhiq1lwOodFrObT30g90kEDJFyviRGER9ts3J0h6MPA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760510806; c=relaxed/simple; bh=tXwa9V+LIKdw/35ZCvIPiXTq/tFNVSOf9yfIyCbNnUk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=acw6Re03WZWFiLNaZ9bG3C9/ksQWd4XewIFE4TkJF6pXcVmOxDaAT60gWfZRTKVhkIovJNkdwmXplIAz34lAsb7Yi9jVC3Lrfcx52ZLhg1GSRXqiBN/RrEyoThpjNyTFTFH/DggCr4Js9/kWQceztlGUNt7eGiwWK945jxaPPRw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Ol3tbLDq; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Ol3tbLDq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1760510805; x=1792046805; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tXwa9V+LIKdw/35ZCvIPiXTq/tFNVSOf9yfIyCbNnUk=; b=Ol3tbLDqyJR0CTDVGzARt5zijJax1zkHaxHpZyezvTtlnrWnYuZWu/AI jlZkH9ZVpnRvL4upCYQalWnFjoqbBfXyblZK++1AUTJBHHLjHe1AUC1S1 03jFlPJEFcX/lZYAv4zDEQbo36FdpezaOANlBD4Ojn+tPnK8R+o3ea0N4 jcGu7drtZHQz1fQPkzUcUjsyM+3g2WjkWkbfPRzgqAcbARn1LDqTEcGKu BHcR0DgAjr1I/0joP45dsyBBD1kn8jUw+H6skzRc8FlF8xFJgX3vOITov 6Q8+R0WGwQ2IoIFv+/kWOT6fCcyB4NbkPPYQRRXVh2uGMOC7gDFts7a0h A==; X-CSE-ConnectionGUID: GFoHDAHGQm6AiMux/VZhHw== X-CSE-MsgGUID: +MidwvOVRk6Fo/O7x6vIDg== X-IronPort-AV: E=McAfee;i="6800,10657,11582"; a="50242519" X-IronPort-AV: E=Sophos;i="6.19,230,1754982000"; d="scan'208";a="50242519" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2025 23:46:44 -0700 X-CSE-ConnectionGUID: WQ9YDugwQA+P/aD98q0MdQ== X-CSE-MsgGUID: cTFYM2IjTfSZX/ZfSwcHHA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,230,1754982000"; d="scan'208";a="182029972" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa006.fm.intel.com with ESMTP; 14 Oct 2025 23:46:41 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Dapeng Mi Subject: [Patch v8 10/12] perf/x86/intel: Update dyn_constranit base on PEBS event precise level Date: Wed, 15 Oct 2025 14:44:20 +0800 Message-Id: <20251015064422.47437-11-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251015064422.47437-1-dapeng1.mi@linux.intel.com> References: <20251015064422.47437-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit arch-PEBS provides CPUIDs to enumerate which counters support PEBS sampling and precise distribution PEBS sampling. Thus PEBS constraints should be dynamically configured base on these counter and precise distribution bitmap instead of defining them statically. Update event dyn_constraint base on PEBS event precise level. Signed-off-by: Dapeng Mi --- arch/x86/events/intel/core.c | 11 +++++++++++ arch/x86/events/intel/ds.c | 1 + 2 files changed, 12 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 41c4af6bd62c..818c197585c6 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4252,6 +4252,8 @@ static int intel_pmu_hw_config(struct perf_event *event) } if (event->attr.precise_ip) { + struct arch_pebs_cap pebs_cap = hybrid(event->pmu, arch_pebs_cap); + if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) return -EINVAL; @@ -4265,6 +4267,15 @@ static int intel_pmu_hw_config(struct perf_event *event) } if (x86_pmu.pebs_aliases) x86_pmu.pebs_aliases(event); + + if (x86_pmu.arch_pebs) { + u64 cntr_mask = hybrid(event->pmu, intel_ctrl) & + ~GLOBAL_CTRL_EN_PERF_METRICS; + u64 pebs_mask = event->attr.precise_ip >= 3 ? + pebs_cap.pdists : pebs_cap.counters; + if (cntr_mask != pebs_mask) + event->hw.dyn_constraint &= pebs_mask; + } } if (needs_branch_stack(event)) { diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 1ec54b0a5d3c..759eff6aa83e 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -3027,6 +3027,7 @@ static void __init intel_arch_pebs_init(void) x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE; x86_pmu.drain_pebs = intel_pmu_drain_arch_pebs; x86_pmu.pebs_capable = ~0ULL; + x86_pmu.flags |= PMU_FL_PEBS_ALL; x86_pmu.pebs_enable = __intel_pmu_pebs_enable; x86_pmu.pebs_disable = __intel_pmu_pebs_disable; -- 2.34.1