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From: Dapeng Mi <dapeng1.mi@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	Eranian Stephane <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	Dapeng Mi <dapeng1.mi@intel.com>,
	Dapeng Mi <dapeng1.mi@linux.intel.com>
Subject: [Patch v8 04/12] perf/x86/intel: Correct large PEBS flag check
Date: Wed, 15 Oct 2025 14:44:14 +0800	[thread overview]
Message-ID: <20251015064422.47437-5-dapeng1.mi@linux.intel.com> (raw)
In-Reply-To: <20251015064422.47437-1-dapeng1.mi@linux.intel.com>

current large PEBS flag check only checks if sample_regs_user contains
unsupported GPRs but doesn't check if sample_regs_intr contains
unsupported GPRs.

Of course, currently PEBS HW supports to sample all perf supported GPRs,
the missed check doesn't cause real issue. But it won't be true any more
after the subsequent patches support to sample SSP register. SSP
sampling is not supported by adaptive PEBS HW and it would be supported
until arch-PEBS HW. So correct this issue.

Fixes: a47ba4d77e12 ("perf/x86: Enable free running PEBS for REGS_USER/INTR")
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
 arch/x86/events/intel/core.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 46a000eb0bb3..c88bcd5d2bc4 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4029,7 +4029,9 @@ static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
 	if (!event->attr.exclude_kernel)
 		flags &= ~PERF_SAMPLE_REGS_USER;
 	if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
-		flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
+		flags &= ~PERF_SAMPLE_REGS_USER;
+	if (event->attr.sample_regs_intr & ~PEBS_GP_REGS)
+		flags &= ~PERF_SAMPLE_REGS_INTR;
 	return flags;
 }
 
-- 
2.34.1


  parent reply	other threads:[~2025-10-15  6:46 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-15  6:44 [Patch v8 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
2025-10-15  6:44 ` [Patch v8 01/12] perf/x86: Remove redundant is_x86_event() prototype Dapeng Mi
2025-10-15  6:44 ` [Patch v8 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss Dapeng Mi
2025-10-22  8:12   ` Mi, Dapeng
2025-10-22 11:24     ` Peter Zijlstra
2025-10-23  2:29       ` Mi, Dapeng
2025-10-15  6:44 ` [Patch v8 03/12] perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call Dapeng Mi
2025-10-15  6:44 ` Dapeng Mi [this message]
2025-10-15  6:44 ` [Patch v8 05/12] perf/x86/intel: Initialize architectural PEBS Dapeng Mi
2025-10-21 15:43   ` Peter Zijlstra
2025-10-22  5:27     ` Mi, Dapeng
2025-10-15  6:44 ` [Patch v8 06/12] perf/x86/intel/ds: Factor out PEBS record processing code to functions Dapeng Mi
2025-10-21 15:49   ` Peter Zijlstra
2025-10-22  5:32     ` Mi, Dapeng
2025-10-22 11:49   ` Peter Zijlstra
2025-10-23  1:06     ` Mi, Dapeng
2025-10-15  6:44 ` [Patch v8 07/12] perf/x86/intel/ds: Factor out PEBS group " Dapeng Mi
2025-10-15  6:44 ` [Patch v8 08/12] perf/x86/intel: Process arch-PEBS records or record fragments Dapeng Mi
2025-10-15  6:44 ` [Patch v8 09/12] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR Dapeng Mi
2025-10-15  6:44 ` [Patch v8 10/12] perf/x86/intel: Update dyn_constranit base on PEBS event precise level Dapeng Mi
2025-10-15  6:44 ` [Patch v8 11/12] perf/x86/intel: Setup PEBS data configuration and enable legacy groups Dapeng Mi
2025-10-15  6:44 ` [Patch v8 12/12] perf/x86/intel: Add counter group support for arch-PEBS Dapeng Mi

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