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Thu, 13 Nov 2025 08:29:07 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 36E0220040; Thu, 13 Nov 2025 08:29:07 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 07A0320043; Thu, 13 Nov 2025 08:29:07 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 13 Nov 2025 08:29:06 +0000 (GMT) From: Thomas Richter To: linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org, namhyung@kernel.org, irogers@google.com Cc: agordeev@linux.ibm.com, gor@linux.ibm.com, sumanthk@linux.ibm.com, hca@linux.ibm.com, japo@linux.ibm.com, Thomas Richter Subject: [PATCH linux-next] perf stat: Regression perf stat -T cpi fails on s390 z/VM guest systems Date: Thu, 13 Nov 2025 09:28:51 +0100 Message-ID: <20251113082852.2902356-1-tmricht@linux.ibm.com> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTA4MDAyMiBTYWx0ZWRfX56jhHZRfXwqN YwpPZOblhwAhfW1oRi0QzzB4VYJsEzdec6wuRpBwutVZgu8v2f9kHza0oDWz2atn1doOBvuXiI0 sBkOaCpoEo2+nraVKMH3rDpk5uh5weIkNScCcwvAZymoyIek1P9OQdLyax+QVX2YfaNvHFeu3Y1 rwjjTSO8I2SpKzZc0cKNJ9QpBbQG6DzPMy6jYt1Sb03kiuy6y4BTOq1kt0bGYSN/aPjL/ANzPMH kkMjeNaJWRUaxUMObJ40eROLCfleOd0eUQ4I5INi3LPx/P6hanc73i/Jdrq4RTeoyqiG9oOqKcZ 8RqV5oaTjCAIw86sy2p3p2JU+GziOOuA7eNwHeTcbSCB0bumrmKTqvTM5adYX4frf7IdZHBSc5b prHDh4IRIQZTkI/qfIM+Er624ybR/Q== X-Authority-Analysis: v=2.4 cv=ZK3aWH7b c=1 sm=1 tr=0 ts=691596d9 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=6UeiqGixMTsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=1XWaLZrsAAAA:8 a=VnNF1IyMAAAA:8 a=1ivgOJDEaqisGwhKzeIA:9 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-ORIG-GUID: DmDJlubNOYXC9cTf-kSwEtj-8tCa7IJD X-Proofpoint-GUID: 9KhmGPdBgR6jbY4QKIwk-3jfrvjzHz_U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-12_06,2025-11-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 phishscore=0 impostorscore=0 spamscore=0 bulkscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2511080022 On s390 z/VM systems (linux guest on s390 LPAR) this happens: # perf test 96 97 96: perf all metricgroups test : FAILED! 97: perf all metrics test : FAILED! This test works on the linux repo: # perf test 95 96 95: perf all metricgroups test : Ok 96: perf all metrics test : Ok On both systems the command # ./perf list --raw-dump metric cpi est_cpi finite_cpi l1mp l2p l3p l4lp l4rp memp prbstate scpl1m \ tlb_miss tlb_percent transaction shows the same list of available metrics. On z/VM the CPU Measurement facilities do not exist: # ll /sys/devices/cpum_cf/events ls: cannot access '/sys/devices/cpum_cf/events': No such file or directory # The json files for s390 define the metric 'cpi' in arch/s390/cf_z16/transaction.json: { "BriefDescription": "Cycles per Instruction", "MetricName": "cpi", "MetricExpr": "CPU_CYCLES / INSTRUCTIONS \ if has_event(INSTRUCTIONS) else 0" }, The macro has_event(INSTRUCTIONS) now refers to a legacy event which always exists. It is always true even when the hardware does not support this event. Change the has_event(xxx) to check for a hardware event not available, for example CPU_CYCLES. Fixes: 0012e0fa221b ("perf jevents: Add legacy-hardware and legacy-cache json") Suggested by: Ian Rogers Signed-off-by: Thomas Richter --- tools/perf/pmu-events/arch/s390/cf_z16/transaction.json | 8 ++++---- tools/perf/pmu-events/arch/s390/cf_z17/transaction.json | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json index 3ab1d3a6638c..26c550621d6a 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json @@ -7,17 +7,17 @@ { "BriefDescription": "Cycles per Instruction", "MetricName": "cpi", - "MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(INSTRUCTIONS) else 0" + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(CPU_CYCLES) else 0" }, { "BriefDescription": "Problem State Instruction Ratio", "MetricName": "prbstate", - "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0" + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if has_event(CPU_CYCLES) else 0" }, { "BriefDescription": "Level One Miss per 100 Instructions", "MetricName": "l1mp", - "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0" + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100 if has_event(CPU_CYCLES) else 0" }, { "BriefDescription": "Percentage sourced from Level 2 cache", @@ -52,7 +52,7 @@ { "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", "MetricName": "est_cpi", - "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS) if has_event(INSTRUCTIONS) else 0" + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS) if has_event(CPU_CYCLES) else 0" }, { "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", diff --git a/tools/perf/pmu-events/arch/s390/cf_z17/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z17/transaction.json index 74df533c8b6f..4d296e0c8934 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z17/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z17/transaction.json @@ -7,17 +7,17 @@ { "BriefDescription": "Cycles per Instruction", "MetricName": "cpi", - "MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(INSTRUCTIONS) else 0" + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(CPU_CYCLES) else 0" }, { "BriefDescription": "Problem State Instruction Ratio", "MetricName": "prbstate", - "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0" + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if has_event(CPU_CYCLES) else 0" }, { "BriefDescription": "Level One Miss per 100 Instructions", "MetricName": "l1mp", - "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0" + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100 if has_event(CPU_CYCLES) else 0" }, { "BriefDescription": "Percentage sourced from Level 2 cache", @@ -52,7 +52,7 @@ { "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", "MetricName": "est_cpi", - "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS) if has_event(INSTRUCTIONS) else 0" + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS) if has_event(CPU_CYCLES) else 0" }, { "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", -- 2.51.1