[PATCH 0/3] perf/x86: Add Airmont NP

[PATCH 0/3] perf/x86: Add Airmont NP

[Martin Schiller]

From the perspective of Intel cstate, PMU and MSR the Airmont NP
(aka Lightning Mountain) is identical to Airmont.

This changes are taken from patched kernel sources of the MaxLinear SDK
which can be found at https://github.com/maxlinear/linux

Martin Schiller (3):
  perf/x86/msr: Add Airmont NP
  perf/x86/intel: Add Airmont NP
  perf/x86/cstate: Add Airmont NP

 arch/x86/events/intel/core.c   | 1 +
 arch/x86/events/intel/cstate.c | 1 +
 arch/x86/events/msr.c          | 1 +
 3 files changed, 3 insertions(+)

-- 
2.47.3

[PATCH 1/3] perf/x86/msr: Add Airmont NP

[Martin Schiller]

Like Airmont, the Airmont NP (aka Intel / MaxLinear Lightning Mountain)
supports SMI_COUNT MSR.

Signed-off-by: Martin Schiller <ms@dev.tdt.de>
---
 arch/x86/events/msr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 7f5007a4752a..8052596b8503 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -78,6 +78,7 @@ static bool test_intel(int idx, void *data)
 	case INTEL_ATOM_SILVERMONT:
 	case INTEL_ATOM_SILVERMONT_D:
 	case INTEL_ATOM_AIRMONT:
+	case INTEL_ATOM_AIRMONT_NP:
 
 	case INTEL_ATOM_GOLDMONT:
 	case INTEL_ATOM_GOLDMONT_D:
-- 
2.47.3

[PATCH 2/3] perf/x86/intel: Add Airmont NP

[Martin Schiller]

The Intel / MaxLinear Airmont NP (aka Lightning Mountain) supports the
same architectual and non-architecural events as Airmont.

Signed-off-by: Martin Schiller <ms@dev.tdt.de>
---
 arch/x86/events/intel/core.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index fe65be0b9d9c..641008590a17 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -7024,6 +7024,7 @@ __init int intel_pmu_init(void)
 	case INTEL_ATOM_SILVERMONT_D:
 	case INTEL_ATOM_SILVERMONT_MID:
 	case INTEL_ATOM_AIRMONT:
+	case INTEL_ATOM_AIRMONT_NP:
 	case INTEL_ATOM_SILVERMONT_MID2:
 		memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
 			sizeof(hw_cache_event_ids));
-- 
2.47.3

[PATCH 3/3] perf/x86/cstate: Add Airmont NP

[Martin Schiller]

From the perspective of Intel cstate residency counters, the Airmont NP
(aka Lightning Mountain) is identical to the Airmont.

Signed-off-by: Martin Schiller <ms@dev.tdt.de>
---
 arch/x86/events/intel/cstate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index ec753e39b007..531dba5a8095 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -599,6 +599,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 	X86_MATCH_VFM(INTEL_ATOM_SILVERMONT,	&slm_cstates),
 	X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_D,	&slm_cstates),
 	X86_MATCH_VFM(INTEL_ATOM_AIRMONT,	&slm_cstates),
+	X86_MATCH_VFM(INTEL_ATOM_AIRMONT_NP,	&slm_cstates),
 
 	X86_MATCH_VFM(INTEL_BROADWELL,		&snb_cstates),
 	X86_MATCH_VFM(INTEL_BROADWELL_D,	&snb_cstates),
-- 
2.47.3

Re: [PATCH 0/3] perf/x86: Add Airmont NP

[Mi, Dapeng]

On 11/24/2025 3:48 PM, Martin Schiller wrote:
> From the perspective of Intel cstate, PMU and MSR the Airmont NP
> (aka Lightning Mountain) is identical to Airmont.
>
> This changes are taken from patched kernel sources of the MaxLinear SDK
> which can be found at https://github.com/maxlinear/linux
>
> Martin Schiller (3):
>   perf/x86/msr: Add Airmont NP
>   perf/x86/intel: Add Airmont NP
>   perf/x86/cstate: Add Airmont NP
>
>  arch/x86/events/intel/core.c   | 1 +
>  arch/x86/events/intel/cstate.c | 1 +
>  arch/x86/events/msr.c          | 1 +
>  3 files changed, 3 insertions(+)

The whole patch-set looks good to me.

Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>