From: Ian Rogers <irogers@google.com>
To: "Thomas Falcon" <thomas.falcon@intel.com>,
"Dapeng Mi" <dapeng1.mi@linux.intel.com>,
"Edward Baker" <edward.baker@intel.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Ingo Molnar" <mingo@redhat.com>,
"Arnaldo Carvalho de Melo" <acme@kernel.org>,
"Namhyung Kim" <namhyung@kernel.org>,
"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
"Jiri Olsa" <jolsa@kernel.org>, "Ian Rogers" <irogers@google.com>,
"Adrian Hunter" <adrian.hunter@intel.com>,
"Andreas Färber" <afaerber@suse.de>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Caleb Biggers" <caleb.biggers@intel.com>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v1 6/9] perf vendor events intel: Update lunarlake events from 1.18 to 1.19
Date: Tue, 2 Dec 2025 08:53:37 -0800 [thread overview]
Message-ID: <20251202165340.555375-7-irogers@google.com> (raw)
In-Reply-To: <20251202165340.555375-1-irogers@google.com>
The updated events were published in:
https://github.com/intel/perfmon/commit/09a0c74b23b5d20adf1f97e5022856568d05494c
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/lunarlake/cache.json | 20 +++++++-------
.../pmu-events/arch/x86/lunarlake/other.json | 1 +
.../arch/x86/lunarlake/pipeline.json | 26 ++++++++++++++++---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
4 files changed, 35 insertions(+), 14 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/cache.json b/tools/perf/pmu-events/arch/x86/lunarlake/cache.json
index 402ca8fc50b6..3d2616be8ec1 100644
--- a/tools/perf/pmu-events/arch/x86/lunarlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/lunarlake/cache.json
@@ -243,7 +243,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of L2 prefetches initiated by either the L2 Stream or AMP that were throttled due to exceeding the XQ threshold set by either XQ_THRESOLD_DTP or XQ_THRESHOLD. Counts on a per core basis.",
+ "BriefDescription": "Counts the number of L2 prefetches initiated by either the L2 Stream or AMP that were throttled due to exceeding the XQ threshold set by either XQ_THRESHOLD_DTP or XQ_THRESHOLD. Counts on a per core basis.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "L2_PREFETCHES_THROTTLED.XQ_THRESH",
@@ -464,7 +464,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of LLC prefetches throttled due to exceeding the XQ threshold set by either XQ_THRESOLD_DTP or LLC_XQ_THRESHOLD. Counts on a per core basis.",
+ "BriefDescription": "Counts the number of LLC prefetches throttled due to exceeding the XQ threshold set by either XQ_THRESHOLD_DTP or LLC_XQ_THRESHOLD. Counts on a per core basis.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x29",
"EventName": "LLC_PREFETCHES_THROTTLED.XQ_THRESH",
@@ -1089,7 +1089,7 @@
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
- "Counter": "0,1,2,3,4,5,6,7",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
@@ -1101,7 +1101,7 @@
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
- "Counter": "0,1,2,3,4,5,6,7",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
@@ -1113,7 +1113,7 @@
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
- "Counter": "0,1,2,3,4,5,6,7",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
@@ -1125,7 +1125,7 @@
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
- "Counter": "0,1,2,3,4,5,6,7",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
@@ -1137,7 +1137,7 @@
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
- "Counter": "0,1,2,3,4,5,6,7",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
@@ -1149,7 +1149,7 @@
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
- "Counter": "0,1,2,3,4,5,6,7",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
@@ -1161,7 +1161,7 @@
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
- "Counter": "0,1,2,3,4,5,6,7",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
@@ -1173,7 +1173,7 @@
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
- "Counter": "0,1,2,3,4,5,6,7",
+ "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/other.json b/tools/perf/pmu-events/arch/x86/lunarlake/other.json
index 1df716442549..164374edf293 100644
--- a/tools/perf/pmu-events/arch/x86/lunarlake/other.json
+++ b/tools/perf/pmu-events/arch/x86/lunarlake/other.json
@@ -178,6 +178,7 @@
"EventCode": "0xf4",
"EventName": "XQ_PROMOTION.ALL",
"SampleAfterValue": "1000003",
+ "UMask": "0x7",
"Unit": "cpu_atom"
},
{
diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json b/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json
index cdaa01e9a57d..97797f7b072e 100644
--- a/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json
@@ -21,8 +21,9 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "Counts the number of active floating point and integer dividers per cycle.",
+ "BriefDescription": "This event is deprecated.",
"Counter": "0,1,2,3,4,5,6,7",
+ "Deprecated": "1",
"EventCode": "0xcd",
"EventName": "ARITH.DIV_OCCUPANCY",
"SampleAfterValue": "1000003",
@@ -30,8 +31,9 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of floating point and integer divider uops executed per cycle.",
+ "BriefDescription": "This event is deprecated.",
"Counter": "0,1,2,3,4,5,6,7",
+ "Deprecated": "1",
"EventCode": "0xcd",
"EventName": "ARITH.DIV_UOPS",
"SampleAfterValue": "1000003",
@@ -1023,6 +1025,15 @@
"UMask": "0x10",
"Unit": "cpu_core"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on secondary integer ports 0,1,2,3.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb3",
+ "EventName": "INT_UOPS_EXECUTED.2ND",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x80",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of uops executed on all Integer ports.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1205,7 +1216,7 @@
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ALL",
"SampleAfterValue": "1000003",
- "UMask": "0x10",
+ "UMask": "0x1f",
"Unit": "cpu_atom"
},
{
@@ -1613,6 +1624,15 @@
"UMask": "0x8",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of issue slots where no uop could issue due to an IQ scoreboard that stalls allocation until a specified older uop retires or (in the case of jump scoreboard) executes. Commonly executed instructions with IQ scoreboards include LFENCE and MFENCE.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x75",
+ "EventName": "SERIALIZATION.IQ_JEU_SCB",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 946471c4d4b7..3bed131e242d 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -22,7 +22,7 @@ GenuineIntel-6-3A,v24,ivybridge,core
GenuineIntel-6-3E,v24,ivytown,core
GenuineIntel-6-2D,v24,jaketown,core
GenuineIntel-6-(57|85),v16,knightslanding,core
-GenuineIntel-6-BD,v1.18,lunarlake,core
+GenuineIntel-6-BD,v1.19,lunarlake,core
GenuineIntel-6-(AA|AC|B5),v1.17,meteorlake,core
GenuineIntel-6-1[AEF],v4,nehalemep,core
GenuineIntel-6-2E,v4,nehalemex,core
--
2.52.0.158.g65b55ccf14-goog
next prev parent reply other threads:[~2025-12-02 16:54 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-02 16:53 [PATCH v1 0/9] Updated Intel events and metric unit fixes Ian Rogers
2025-12-02 16:53 ` [PATCH v1 1/9] perf vendor events intel: Update alderlake events from 1.34 to 1.35 Ian Rogers
2025-12-02 16:53 ` [PATCH v1 2/9] perf vendor events intel: Update arrowlake events from 1.13 to 1.14 Ian Rogers
2025-12-02 16:53 ` [PATCH v1 3/9] perf vendor events intel: Update cascadelakex metric units Ian Rogers
2025-12-02 16:53 ` [PATCH v1 4/9] perf vendor events intel: Update graniterapids events from 1.15 to 1.16 Ian Rogers
2025-12-02 16:53 ` [PATCH v1 5/9] perf vendor events intel: Update icelakex events from 1.28 to 1.30 Ian Rogers
2025-12-02 16:53 ` Ian Rogers [this message]
2025-12-02 16:53 ` [PATCH v1 7/9] perf vendor events intel: Update meteorlake events from 1.17 to 1.18 Ian Rogers
2025-12-02 16:53 ` [PATCH v1 8/9] perf vendor events intel: Update pantherlake events from 1.00 to 1.02 Ian Rogers
2025-12-02 16:53 ` [PATCH v1 9/9] perf vendor events intel: Update sierraforest events from 1.12 to 1.13 Ian Rogers
2025-12-03 7:12 ` [PATCH v1 0/9] Updated Intel events and metric unit fixes Mi, Dapeng
2025-12-04 19:10 ` Namhyung Kim
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