[PATCH 0/2] perf arm_spe: Minor event configs housekeeping

[PATCH 0/2] perf arm_spe: Minor event configs housekeeping

[Leo Yan]

This series is to clean up event configs and update the doc for default
events used for Arm SPE.

A quick verifying on Orion6 board with commands:

  perf c2c record -e spe-load -- test
  perf c2c record -e spe-store -- test

Signed-off-by: Leo Yan <leo.yan@arm.com>
---
Leo Yan (2):
      perf mem: Simplify Arm SPE event config
      perf c2c: Update documentation for Arm SPE events

 tools/perf/Documentation/perf-c2c.txt   | 7 ++++++-
 tools/perf/arch/arm64/util/mem-events.c | 4 ++--
 2 files changed, 8 insertions(+), 3 deletions(-)
---
base-commit: cb015814f8b6eebcbb8e46e111d108892c5e6821
change-id: 20251212-perf_c2c_update_event-76d4eddebd23

Best regards,
-- 
Leo Yan <leo.yan@arm.com>

[PATCH 1/2] perf mem: Simplify Arm SPE event config

[Leo Yan]

Since configuration fields default to zero, the zero assignments are
redundant, remove them.

Signed-off-by: Leo Yan <leo.yan@arm.com>
---
 tools/perf/arch/arm64/util/mem-events.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/perf/arch/arm64/util/mem-events.c b/tools/perf/arch/arm64/util/mem-events.c
index 9f8da7937255cc9b14c3c58a1119b40bd0c76f6b..eaf00e0609c6c1b7d939a02fe3794471d1ed119b 100644
--- a/tools/perf/arch/arm64/util/mem-events.c
+++ b/tools/perf/arch/arm64/util/mem-events.c
@@ -6,7 +6,7 @@
 #define E(t, n, s, l, a) { .tag = t, .name = n, .event_name = s, .ldlat = l, .aux_event = a }
 
 struct perf_mem_event perf_mem_events_arm[PERF_MEM_EVENTS__MAX] = {
-	E("spe-load",	"%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=0,min_latency=%u/",	NULL,	true,	0),
-	E("spe-store",	"%s/ts_enable=1,pa_enable=1,load_filter=0,store_filter=1/",			NULL,	false,	0),
+	E("spe-load",	"%s/ts_enable=1,pa_enable=1,load_filter=1,min_latency=%u/",	NULL,	true,	0),
+	E("spe-store",	"%s/ts_enable=1,pa_enable=1,store_filter=1/",			NULL,	false,	0),
 	E("spe-ldst",	"%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=%u/",	NULL,	true,	0),
 };

-- 
2.34.1

Re: [PATCH 1/2] perf mem: Simplify Arm SPE event config

[James Clark]

On 12/12/2025 14:44, Leo Yan wrote:
> Since configuration fields default to zero, the zero assignments are
> redundant, remove them.
> 
> Signed-off-by: Leo Yan <leo.yan@arm.com>
> ---
>   tools/perf/arch/arm64/util/mem-events.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/perf/arch/arm64/util/mem-events.c b/tools/perf/arch/arm64/util/mem-events.c
> index 9f8da7937255cc9b14c3c58a1119b40bd0c76f6b..eaf00e0609c6c1b7d939a02fe3794471d1ed119b 100644
> --- a/tools/perf/arch/arm64/util/mem-events.c
> +++ b/tools/perf/arch/arm64/util/mem-events.c
> @@ -6,7 +6,7 @@
>   #define E(t, n, s, l, a) { .tag = t, .name = n, .event_name = s, .ldlat = l, .aux_event = a }
>   
>   struct perf_mem_event perf_mem_events_arm[PERF_MEM_EVENTS__MAX] = {
> -	E("spe-load",	"%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=0,min_latency=%u/",	NULL,	true,	0),
> -	E("spe-store",	"%s/ts_enable=1,pa_enable=1,load_filter=0,store_filter=1/",			NULL,	false,	0),
> +	E("spe-load",	"%s/ts_enable=1,pa_enable=1,load_filter=1,min_latency=%u/",	NULL,	true,	0),
> +	E("spe-store",	"%s/ts_enable=1,pa_enable=1,store_filter=1/",			NULL,	false,	0),
>   	E("spe-ldst",	"%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=%u/",	NULL,	true,	0),
>   };
> 

Reviewed-by: James Clark <james.clark@linaro.org>

[PATCH 2/2] perf c2c: Update documentation for Arm SPE events

[Leo Yan]

Document the default Arm SPE events used by the perf c2c tool.  Make a
minor adjustment to the PowerPC entry for formatting consistency.

Suggested-by: Al Grant <al.grant@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
---
 tools/perf/Documentation/perf-c2c.txt | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/perf/Documentation/perf-c2c.txt b/tools/perf/Documentation/perf-c2c.txt
index 40b0f71a2c44eb642ff3bb234631a614b7c4fc9d..b765ae2511d2418a63092fb8a90a61faa335ac91 100644
--- a/tools/perf/Documentation/perf-c2c.txt
+++ b/tools/perf/Documentation/perf-c2c.txt
@@ -170,11 +170,16 @@ following on AMD:
 
   ibs_op//
 
-and following on PowerPC:
+following on PowerPC:
 
   cpu/mem-loads/
   cpu/mem-stores/
 
+following on Arm:
+
+  arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,min_latency=30/
+  arm_spe_0/ts_enable=1,pa_enable=1,store_filter=1/
+
 User can pass any 'perf record' option behind '--' mark, like (to enable
 callchains and system wide monitoring):
 

-- 
2.34.1

Re: [PATCH 2/2] perf c2c: Update documentation for Arm SPE events

[James Clark]

On 12/12/2025 14:44, Leo Yan wrote:
> Document the default Arm SPE events used by the perf c2c tool.  Make a
> minor adjustment to the PowerPC entry for formatting consistency.
> 
> Suggested-by: Al Grant <al.grant@arm.com>
> Signed-off-by: Leo Yan <leo.yan@arm.com>
> ---
>   tools/perf/Documentation/perf-c2c.txt | 7 ++++++-
>   1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/perf/Documentation/perf-c2c.txt b/tools/perf/Documentation/perf-c2c.txt
> index 40b0f71a2c44eb642ff3bb234631a614b7c4fc9d..b765ae2511d2418a63092fb8a90a61faa335ac91 100644
> --- a/tools/perf/Documentation/perf-c2c.txt
> +++ b/tools/perf/Documentation/perf-c2c.txt
> @@ -170,11 +170,16 @@ following on AMD:
>   
>     ibs_op//
>   
> -and following on PowerPC:
> +following on PowerPC:
>   
>     cpu/mem-loads/
>     cpu/mem-stores/
>   
> +following on Arm:
> +
> +  arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,min_latency=30/
> +  arm_spe_0/ts_enable=1,pa_enable=1,store_filter=1/
> +

Technically there's 3 different ones on Arm because 
PERF_MEM_EVENTS__LOAD_STORE is also supported. Although I question the 
usefulness of these without labels or any text to say what the 
difference is, but that's an existing problem.

>   User can pass any 'perf record' option behind '--' mark, like (to enable
>   callchains and system wide monitoring):
>   
>