* [PATCH v2 0/2] perf arm_spe: Minor event configs housekeeping
@ 2025-12-12 17:24 Leo Yan
2025-12-12 17:24 ` [PATCH v2 1/2] perf mem: Simplify Arm SPE event config Leo Yan
2025-12-12 17:25 ` [PATCH v2 2/2] perf c2c: Update documentation for adding memory event table Leo Yan
0 siblings, 2 replies; 4+ messages in thread
From: Leo Yan @ 2025-12-12 17:24 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Namhyung Kim, Ian Rogers, James Clark,
Mike Leach, Will Deacon, Mark Rutland, Jiri Olsa, Adrian Hunter,
Al Grant
Cc: linux-arm-kernel, linux-perf-users, linux-kernel, Leo Yan
This series is to clean up event configs and update the doc for the
memory events and related options on different archs.
A quick verifying on Orion6 board with commands:
perf c2c record -e spe-load -- test
perf c2c record -e spe-store -- test
Signed-off-by: Leo Yan <leo.yan@arm.com>
---
Changes in v2:
- Updated document with using table for memory events (James).
- Link to v1: https://lore.kernel.org/r/20251212-perf_c2c_update_event-v1-0-29a26c7a949b@arm.com
---
Leo Yan (2):
perf mem: Simplify Arm SPE event config
perf c2c: Update documentation for adding memory event table
tools/perf/Documentation/perf-c2c.txt | 51 ++++++++++++++++++++++++---------
tools/perf/arch/arm64/util/mem-events.c | 4 +--
2 files changed, 39 insertions(+), 16 deletions(-)
---
base-commit: cb015814f8b6eebcbb8e46e111d108892c5e6821
change-id: 20251212-perf_c2c_update_event-76d4eddebd23
Best regards,
--
Leo Yan <leo.yan@arm.com>
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v2 1/2] perf mem: Simplify Arm SPE event config 2025-12-12 17:24 [PATCH v2 0/2] perf arm_spe: Minor event configs housekeeping Leo Yan @ 2025-12-12 17:24 ` Leo Yan 2025-12-12 17:25 ` [PATCH v2 2/2] perf c2c: Update documentation for adding memory event table Leo Yan 1 sibling, 0 replies; 4+ messages in thread From: Leo Yan @ 2025-12-12 17:24 UTC (permalink / raw) To: Arnaldo Carvalho de Melo, Namhyung Kim, Ian Rogers, James Clark, Mike Leach, Will Deacon, Mark Rutland, Jiri Olsa, Adrian Hunter, Al Grant Cc: linux-arm-kernel, linux-perf-users, linux-kernel, Leo Yan Since configuration fields default to zero, the zero assignments are redundant, remove them. Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Leo Yan <leo.yan@arm.com> --- tools/perf/arch/arm64/util/mem-events.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/perf/arch/arm64/util/mem-events.c b/tools/perf/arch/arm64/util/mem-events.c index 9f8da7937255cc9b14c3c58a1119b40bd0c76f6b..eaf00e0609c6c1b7d939a02fe3794471d1ed119b 100644 --- a/tools/perf/arch/arm64/util/mem-events.c +++ b/tools/perf/arch/arm64/util/mem-events.c @@ -6,7 +6,7 @@ #define E(t, n, s, l, a) { .tag = t, .name = n, .event_name = s, .ldlat = l, .aux_event = a } struct perf_mem_event perf_mem_events_arm[PERF_MEM_EVENTS__MAX] = { - E("spe-load", "%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=0,min_latency=%u/", NULL, true, 0), - E("spe-store", "%s/ts_enable=1,pa_enable=1,load_filter=0,store_filter=1/", NULL, false, 0), + E("spe-load", "%s/ts_enable=1,pa_enable=1,load_filter=1,min_latency=%u/", NULL, true, 0), + E("spe-store", "%s/ts_enable=1,pa_enable=1,store_filter=1/", NULL, false, 0), E("spe-ldst", "%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=%u/", NULL, true, 0), }; -- 2.34.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 2/2] perf c2c: Update documentation for adding memory event table 2025-12-12 17:24 [PATCH v2 0/2] perf arm_spe: Minor event configs housekeeping Leo Yan 2025-12-12 17:24 ` [PATCH v2 1/2] perf mem: Simplify Arm SPE event config Leo Yan @ 2025-12-12 17:25 ` Leo Yan 2025-12-15 8:40 ` James Clark 1 sibling, 1 reply; 4+ messages in thread From: Leo Yan @ 2025-12-12 17:25 UTC (permalink / raw) To: Arnaldo Carvalho de Melo, Namhyung Kim, Ian Rogers, James Clark, Mike Leach, Will Deacon, Mark Rutland, Jiri Olsa, Adrian Hunter, Al Grant Cc: linux-arm-kernel, linux-perf-users, linux-kernel, Leo Yan Users may occasionally need to see which options are applied to memory events. This helps to understand the behavior of "perf c2c" and "perf mem", and provides guidance for configuring memory event options directly. Add a table to track memory events and their corresponding options, and include the Arm SPE events in it. Suggested-by: Al Grant <al.grant@arm.com> Signed-off-by: Leo Yan <leo.yan@arm.com> --- tools/perf/Documentation/perf-c2c.txt | 51 +++++++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 14 deletions(-) diff --git a/tools/perf/Documentation/perf-c2c.txt b/tools/perf/Documentation/perf-c2c.txt index 40b0f71a2c44eb642ff3bb234631a614b7c4fc9d..e57a122b8719f1b2e20dd509959fc1563a6c20fd 100644 --- a/tools/perf/Documentation/perf-c2c.txt +++ b/tools/perf/Documentation/perf-c2c.txt @@ -160,20 +160,43 @@ Following perf record options are configured by default: -W,-d,--phys-data,--sample-cpu -Unless specified otherwise with '-e' option, following events are monitored by -default on Intel: - - cpu/mem-loads,ldlat=30/P - cpu/mem-stores/P - -following on AMD: - - ibs_op// - -and following on PowerPC: - - cpu/mem-loads/ - cpu/mem-stores/ +The following table lists the events monitored on different architectures. +Unless specified otherwise with the -e option, the tool will select the +default events. + + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ + | Arch | Configuration | Options | Events | + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ + | Intel | Default | -e ldlat-loads | cpu/mem-loads,ldlat=30/P | + | | | -e ldlat-stores | cpu/mem-stores/P | + | |---------------+-----------------+--------------------------------------------------------------------------------+ + | | Load only | -e ldlat-loads | cpu/mem-loads,ldlat=30/P | + | |---------------+-----------------+--------------------------------------------------------------------------------+ + | | Store only | -e ldlat-stores | cpu/mem-stores/P | + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ + | Intel | Default | -e ldlat-loads | {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P | + | with | | -e ldlat-stores | cpu/mem-stores/P | + | AUX |--------------+------------------+--------------------------------------------------------------------------------+ + | | Load only | -e ldlat-loads | {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P | + | |---------------+-----------------+--------------------------------------------------------------------------------+ + | | Store only | -e ldlat-stores | cpu/mem-stores/P | + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ + | AMD | Default | -e mem-ldst | ibs_op// (without latency support) | + | | | | ibs_op/ldlat=30/ (with latency support) | + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ + | PowerPC| Default | -e ldlat-loads | cpu/mem-loads/ | + | | | -e ldlat-stores | cpu/mem-stores/ | + | |---------------+-----------------+--------------------------------------------------------------------------------+ + | | Load only | -e ldlat-loads | cpu/mem-loads/ | + | |---------------+-----------------+--------------------------------------------------------------------------------+ + | | Store only | -e ldlat-stores | cpu/mem-stores/ | + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ + | Arm | Default | -e spe-ldst | arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=30/ | + | SPE |---------------+-----------------+--------------------------------------------------------------------------------+ + | | Load only | -e spe-load | arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,min_latency=30/ | + | |---------------+-----------------+--------------------------------------------------------------------------------+ + | | Store only | -e spe-store | arm_spe_0/ts_enable=1,pa_enable=1,store_filter=1/ | + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ User can pass any 'perf record' option behind '--' mark, like (to enable callchains and system wide monitoring): -- 2.34.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2 2/2] perf c2c: Update documentation for adding memory event table 2025-12-12 17:25 ` [PATCH v2 2/2] perf c2c: Update documentation for adding memory event table Leo Yan @ 2025-12-15 8:40 ` James Clark 0 siblings, 0 replies; 4+ messages in thread From: James Clark @ 2025-12-15 8:40 UTC (permalink / raw) To: Leo Yan Cc: linux-arm-kernel, linux-perf-users, linux-kernel, Arnaldo Carvalho de Melo, Namhyung Kim, Ian Rogers, Mike Leach, Will Deacon, Mark Rutland, Jiri Olsa, Adrian Hunter, Al Grant On 12/12/2025 19:25, Leo Yan wrote: > Users may occasionally need to see which options are applied to memory > events. This helps to understand the behavior of "perf c2c" and > "perf mem", and provides guidance for configuring memory event options > directly. > > Add a table to track memory events and their corresponding options, and > include the Arm SPE events in it. > > Suggested-by: Al Grant <al.grant@arm.com> > Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: James Clark <james.clark@linaro.org> > --- > tools/perf/Documentation/perf-c2c.txt | 51 +++++++++++++++++++++++++---------- > 1 file changed, 37 insertions(+), 14 deletions(-) > > diff --git a/tools/perf/Documentation/perf-c2c.txt b/tools/perf/Documentation/perf-c2c.txt > index 40b0f71a2c44eb642ff3bb234631a614b7c4fc9d..e57a122b8719f1b2e20dd509959fc1563a6c20fd 100644 > --- a/tools/perf/Documentation/perf-c2c.txt > +++ b/tools/perf/Documentation/perf-c2c.txt > @@ -160,20 +160,43 @@ Following perf record options are configured by default: > > -W,-d,--phys-data,--sample-cpu > > -Unless specified otherwise with '-e' option, following events are monitored by > -default on Intel: > - > - cpu/mem-loads,ldlat=30/P > - cpu/mem-stores/P > - > -following on AMD: > - > - ibs_op// > - > -and following on PowerPC: > - > - cpu/mem-loads/ > - cpu/mem-stores/ > +The following table lists the events monitored on different architectures. > +Unless specified otherwise with the -e option, the tool will select the > +default events. > + > + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ > + | Arch | Configuration | Options | Events | > + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ > + | Intel | Default | -e ldlat-loads | cpu/mem-loads,ldlat=30/P | > + | | | -e ldlat-stores | cpu/mem-stores/P | > + | |---------------+-----------------+--------------------------------------------------------------------------------+ > + | | Load only | -e ldlat-loads | cpu/mem-loads,ldlat=30/P | > + | |---------------+-----------------+--------------------------------------------------------------------------------+ > + | | Store only | -e ldlat-stores | cpu/mem-stores/P | > + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ > + | Intel | Default | -e ldlat-loads | {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P | > + | with | | -e ldlat-stores | cpu/mem-stores/P | > + | AUX |--------------+------------------+--------------------------------------------------------------------------------+ > + | | Load only | -e ldlat-loads | {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P | > + | |---------------+-----------------+--------------------------------------------------------------------------------+ > + | | Store only | -e ldlat-stores | cpu/mem-stores/P | > + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ > + | AMD | Default | -e mem-ldst | ibs_op// (without latency support) | > + | | | | ibs_op/ldlat=30/ (with latency support) | > + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ > + | PowerPC| Default | -e ldlat-loads | cpu/mem-loads/ | > + | | | -e ldlat-stores | cpu/mem-stores/ | > + | |---------------+-----------------+--------------------------------------------------------------------------------+ > + | | Load only | -e ldlat-loads | cpu/mem-loads/ | > + | |---------------+-----------------+--------------------------------------------------------------------------------+ > + | | Store only | -e ldlat-stores | cpu/mem-stores/ | > + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ > + | Arm | Default | -e spe-ldst | arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=30/ | > + | SPE |---------------+-----------------+--------------------------------------------------------------------------------+ > + | | Load only | -e spe-load | arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,min_latency=30/ | > + | |---------------+-----------------+--------------------------------------------------------------------------------+ > + | | Store only | -e spe-store | arm_spe_0/ts_enable=1,pa_enable=1,store_filter=1/ | > + +--------+---------------+-----------------+--------------------------------------------------------------------------------+ > > User can pass any 'perf record' option behind '--' mark, like (to enable > callchains and system wide monitoring): > ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2025-12-15 8:40 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-12-12 17:24 [PATCH v2 0/2] perf arm_spe: Minor event configs housekeeping Leo Yan 2025-12-12 17:24 ` [PATCH v2 1/2] perf mem: Simplify Arm SPE event config Leo Yan 2025-12-12 17:25 ` [PATCH v2 2/2] perf c2c: Update documentation for adding memory event table Leo Yan 2025-12-15 8:40 ` James Clark
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