* [PATCH 2/3] perf/x86/intel/cstate: Add Nova Lake support
2025-12-15 18:25 [PATCH 1/3] perf/x86/intel/cstate: Add Wildcat Lake support Zide Chen
@ 2025-12-15 18:25 ` Zide Chen
2025-12-15 18:25 ` [PATCH 3/3] perf/x86/intel/cstate: Add Diamond Rapids support Zide Chen
2025-12-16 1:51 ` [PATCH 1/3] perf/x86/intel/cstate: Add Wildcat Lake support Mi, Dapeng
2 siblings, 0 replies; 4+ messages in thread
From: Zide Chen @ 2025-12-15 18:25 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Artem Bityutskiy,
Srinivas Pandruvada, Dapeng Mi, Xudong Hao, Falcon Thomas,
Zide Chen
Similar to Lunar Lake and Panther Lake, Nova Lake supports CC1/CC6/CC7
and PC2/PC6/PC10 residency counters; it also adds support for MC6.
Signed-off-by: Zide Chen <zide.chen@intel.com>
---
arch/x86/events/intel/cstate.c | 29 ++++++++++++++++++++++-------
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index b719b0a68a2a..008f8ea59315 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -41,7 +41,7 @@
* MSR_CORE_C1_RES: CORE C1 Residency Counter
* perf code: 0x00
* Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
- * MTL,SRF,GRR,ARL,LNL,PTL,WCL
+ * MTL,SRF,GRR,ARL,LNL,PTL,WCL,NVL
* Scope: Core (each processor core has a MSR)
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
* perf code: 0x01
@@ -53,19 +53,20 @@
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
* TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
- * GRR,ARL,LNL,PTL,WCL
+ * GRR,ARL,LNL,PTL,WCL,NVL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
* Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
* ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL,
- * PTL,WCL
+ * PTL,WCL,NVL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
* KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
- * RPL,SPR,MTL,ARL,LNL,SRF,PTL,WCL
+ * RPL,SPR,MTL,ARL,LNL,SRF,PTL,WCL,
+ * NVL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
@@ -78,7 +79,7 @@
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
* TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
- * ARL,LNL,PTL,WCL
+ * ARL,LNL,PTL,WCL,NVL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
@@ -98,11 +99,11 @@
* perf code: 0x06
* Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
* TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL,
- * WCL
+ * WCL,NVL
* Scope: Package (physical package)
* MSR_MODULE_C6_RES_MS: Module C6 Residency Counter.
* perf code: 0x00
- * Available model: SRF,GRR
+ * Available model: SRF,GRR,NVL
* Scope: A cluster of cores shared L2 cache
*
*/
@@ -528,6 +529,18 @@ static const struct cstate_model lnl_cstates __initconst = {
BIT(PERF_CSTATE_PKG_C10_RES),
};
+static const struct cstate_model nvl_cstates __initconst = {
+ .core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
+ BIT(PERF_CSTATE_CORE_C6_RES) |
+ BIT(PERF_CSTATE_CORE_C7_RES),
+
+ .module_events = BIT(PERF_CSTATE_MODULE_C6_RES),
+
+ .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
+ BIT(PERF_CSTATE_PKG_C6_RES) |
+ BIT(PERF_CSTATE_PKG_C10_RES),
+};
+
static const struct cstate_model slm_cstates __initconst = {
.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
BIT(PERF_CSTATE_CORE_C6_RES),
@@ -656,6 +669,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_cstates),
X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &lnl_cstates),
X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &lnl_cstates),
+ X86_MATCH_VFM(INTEL_NOVALAKE, &nvl_cstates),
+ X86_MATCH_VFM(INTEL_NOVALAKE_L, &nvl_cstates),
{ },
};
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
--
2.52.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 3/3] perf/x86/intel/cstate: Add Diamond Rapids support
2025-12-15 18:25 [PATCH 1/3] perf/x86/intel/cstate: Add Wildcat Lake support Zide Chen
2025-12-15 18:25 ` [PATCH 2/3] perf/x86/intel/cstate: Add Nova " Zide Chen
@ 2025-12-15 18:25 ` Zide Chen
2025-12-16 1:51 ` [PATCH 1/3] perf/x86/intel/cstate: Add Wildcat Lake support Mi, Dapeng
2 siblings, 0 replies; 4+ messages in thread
From: Zide Chen @ 2025-12-15 18:25 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Artem Bityutskiy,
Srinivas Pandruvada, Dapeng Mi, Xudong Hao, Falcon Thomas,
Zide Chen
From a C-state residency profiling perspective, Diamond Rapids is
similar to SRF and GNR, supporting core C1/C6, module C6, and
package C2/C6 residency counters. Similar to CWF, the C1E residency
can be accessed via PMT only.
Signed-off-by: Zide Chen <zide.chen@intel.com>
---
arch/x86/events/intel/cstate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 008f8ea59315..1e2658b60d91 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -652,6 +652,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &icx_cstates),
X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, &icx_cstates),
X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, &icx_cstates),
+ X86_MATCH_VFM(INTEL_DIAMONDRAPIDS_X, &srf_cstates),
X86_MATCH_VFM(INTEL_TIGERLAKE_L, &icl_cstates),
X86_MATCH_VFM(INTEL_TIGERLAKE, &icl_cstates),
--
2.52.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH 1/3] perf/x86/intel/cstate: Add Wildcat Lake support
2025-12-15 18:25 [PATCH 1/3] perf/x86/intel/cstate: Add Wildcat Lake support Zide Chen
2025-12-15 18:25 ` [PATCH 2/3] perf/x86/intel/cstate: Add Nova " Zide Chen
2025-12-15 18:25 ` [PATCH 3/3] perf/x86/intel/cstate: Add Diamond Rapids support Zide Chen
@ 2025-12-16 1:51 ` Mi, Dapeng
2 siblings, 0 replies; 4+ messages in thread
From: Mi, Dapeng @ 2025-12-16 1:51 UTC (permalink / raw)
To: Zide Chen, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Artem Bityutskiy,
Srinivas Pandruvada, Xudong Hao, Falcon Thomas
The whole patch-set looks good to me. Thanks.
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
On 12/16/2025 2:25 AM, Zide Chen wrote:
> Wildcat Lake (WCL) is a low-power variant of Panther Lake. From a
> C-state profiling perspective, it supports the same residency counters:
> CC1/CC6/CC7 and PC2/PC6/PC10.
>
> Signed-off-by: Zide Chen <zide.chen@intel.com>
> ---
> arch/x86/events/intel/cstate.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
> index fa67fda6e45b..b719b0a68a2a 100644
> --- a/arch/x86/events/intel/cstate.c
> +++ b/arch/x86/events/intel/cstate.c
> @@ -41,7 +41,7 @@
> * MSR_CORE_C1_RES: CORE C1 Residency Counter
> * perf code: 0x00
> * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
> - * MTL,SRF,GRR,ARL,LNL,PTL
> + * MTL,SRF,GRR,ARL,LNL,PTL,WCL
> * Scope: Core (each processor core has a MSR)
> * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
> * perf code: 0x01
> @@ -53,19 +53,19 @@
> * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
> * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
> * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
> - * GRR,ARL,LNL,PTL
> + * GRR,ARL,LNL,PTL,WCL
> * Scope: Core
> * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
> * perf code: 0x03
> * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
> * ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL,
> - * PTL
> + * PTL,WCL
> * Scope: Core
> * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
> * perf code: 0x00
> * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
> * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
> - * RPL,SPR,MTL,ARL,LNL,SRF,PTL
> + * RPL,SPR,MTL,ARL,LNL,SRF,PTL,WCL
> * Scope: Package (physical package)
> * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
> * perf code: 0x01
> @@ -78,7 +78,7 @@
> * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
> * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
> * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
> - * ARL,LNL,PTL
> + * ARL,LNL,PTL,WCL
> * Scope: Package (physical package)
> * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
> * perf code: 0x03
> @@ -97,7 +97,8 @@
> * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
> * perf code: 0x06
> * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
> - * TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL
> + * TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL,
> + * WCL
> * Scope: Package (physical package)
> * MSR_MODULE_C6_RES_MS: Module C6 Residency Counter.
> * perf code: 0x00
> @@ -654,6 +655,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
> X86_MATCH_VFM(INTEL_ARROWLAKE_U, &adl_cstates),
> X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_cstates),
> X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &lnl_cstates),
> + X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &lnl_cstates),
> { },
> };
> MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
^ permalink raw reply [flat|nested] 4+ messages in thread