From: Zide Chen <zide.chen@intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Dapeng Mi <dapeng1.mi@linux.intel.com>,
Zide Chen <zide.chen@intel.com>,
Xudong Hao <xudong.hao@intel.com>,
Falcon Thomas <thomas.falcon@intel.com>
Subject: [PATCH V2 07/13] perf/x86/intel/uncore: Add freerunning event descriptor helper macro
Date: Wed, 31 Dec 2025 14:42:24 -0800 [thread overview]
Message-ID: <20251231224233.113839-8-zide.chen@intel.com> (raw)
In-Reply-To: <20251231224233.113839-1-zide.chen@intel.com>
Freerunning counter events are repetitive: the event code is fixed to
0xff, the unit is always "MiB", and the scale is identical across all
counters on a given PMON unit.
Introduce a new helper macro, INTEL_UNCORE_FR_EVENT_DESC(), to populate
the event, scale, and unit descriptor triplet. This reduces duplicated
lines and improves readability.
No functional change intended.
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
---
arch/x86/events/intel/uncore_snbep.c | 95 ++++++++--------------------
1 file changed, 28 insertions(+), 67 deletions(-)
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index df173534637a..09a3bdbd188a 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -4068,34 +4068,24 @@ static struct freerunning_counters skx_iio_freerunning[] = {
[SKX_IIO_MSR_UTIL] = { 0xb08, 0x1, 0x10, 8, 36 },
};
+#define INTEL_UNCORE_FR_EVENT_DESC(name, umask, scl) \
+ INTEL_UNCORE_EVENT_DESC(name, \
+ "event=0xff,umask=" __stringify(umask)), \
+ INTEL_UNCORE_EVENT_DESC(name.scale, __stringify(scl)), \
+ INTEL_UNCORE_EVENT_DESC(name.unit, "MiB")
+
static struct uncore_event_desc skx_uncore_iio_freerunning_events[] = {
/* Free-Running IO CLOCKS Counter */
INTEL_UNCORE_EVENT_DESC(ioclk, "event=0xff,umask=0x10"),
/* Free-Running IIO BANDWIDTH Counters */
- INTEL_UNCORE_EVENT_DESC(bw_in_port0, "event=0xff,umask=0x20"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port0.scale, "3.814697266e-6"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port0.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port1, "event=0xff,umask=0x21"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port1.scale, "3.814697266e-6"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port1.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port2, "event=0xff,umask=0x22"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port2.scale, "3.814697266e-6"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port2.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port3, "event=0xff,umask=0x23"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port3.scale, "3.814697266e-6"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port3.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(bw_out_port0, "event=0xff,umask=0x24"),
- INTEL_UNCORE_EVENT_DESC(bw_out_port0.scale, "3.814697266e-6"),
- INTEL_UNCORE_EVENT_DESC(bw_out_port0.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(bw_out_port1, "event=0xff,umask=0x25"),
- INTEL_UNCORE_EVENT_DESC(bw_out_port1.scale, "3.814697266e-6"),
- INTEL_UNCORE_EVENT_DESC(bw_out_port1.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(bw_out_port2, "event=0xff,umask=0x26"),
- INTEL_UNCORE_EVENT_DESC(bw_out_port2.scale, "3.814697266e-6"),
- INTEL_UNCORE_EVENT_DESC(bw_out_port2.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(bw_out_port3, "event=0xff,umask=0x27"),
- INTEL_UNCORE_EVENT_DESC(bw_out_port3.scale, "3.814697266e-6"),
- INTEL_UNCORE_EVENT_DESC(bw_out_port3.unit, "MiB"),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, 3.814697266e-6),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, 3.814697266e-6),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, 3.814697266e-6),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, 3.814697266e-6),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_out_port0, 0x24, 3.814697266e-6),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_out_port1, 0x25, 3.814697266e-6),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_out_port2, 0x26, 3.814697266e-6),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_out_port3, 0x27, 3.814697266e-6),
/* Free-running IIO UTILIZATION Counters */
INTEL_UNCORE_EVENT_DESC(util_in_port0, "event=0xff,umask=0x30"),
INTEL_UNCORE_EVENT_DESC(util_out_port0, "event=0xff,umask=0x31"),
@@ -4910,30 +4900,14 @@ static struct uncore_event_desc snr_uncore_iio_freerunning_events[] = {
/* Free-Running IIO CLOCKS Counter */
INTEL_UNCORE_EVENT_DESC(ioclk, "event=0xff,umask=0x10"),
/* Free-Running IIO BANDWIDTH IN Counters */
- INTEL_UNCORE_EVENT_DESC(bw_in_port0, "event=0xff,umask=0x20"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port0.scale, "3.0517578125e-5"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port0.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port1, "event=0xff,umask=0x21"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port1.scale, "3.0517578125e-5"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port1.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port2, "event=0xff,umask=0x22"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port2.scale, "3.0517578125e-5"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port2.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port3, "event=0xff,umask=0x23"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port3.scale, "3.0517578125e-5"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port3.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port4, "event=0xff,umask=0x24"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port4.scale, "3.0517578125e-5"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port4.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port5, "event=0xff,umask=0x25"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port5.scale, "3.0517578125e-5"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port5.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port6, "event=0xff,umask=0x26"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port6.scale, "3.0517578125e-5"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port6.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port7, "event=0xff,umask=0x27"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port7.scale, "3.0517578125e-5"),
- INTEL_UNCORE_EVENT_DESC(bw_in_port7.unit, "MiB"),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, 3.0517578125e-5),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, 3.0517578125e-5),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, 3.0517578125e-5),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, 3.0517578125e-5),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_in_port4, 0x24, 3.0517578125e-5),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_in_port5, 0x25, 3.0517578125e-5),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_in_port6, 0x26, 3.0517578125e-5),
+ INTEL_UNCORE_FR_EVENT_DESC(bw_in_port7, 0x27, 3.0517578125e-5),
{ /* end: all zeroes */ },
};
@@ -5266,12 +5240,8 @@ static struct freerunning_counters snr_imc_freerunning[] = {
static struct uncore_event_desc snr_uncore_imc_freerunning_events[] = {
INTEL_UNCORE_EVENT_DESC(dclk, "event=0xff,umask=0x10"),
- INTEL_UNCORE_EVENT_DESC(read, "event=0xff,umask=0x20"),
- INTEL_UNCORE_EVENT_DESC(read.scale, "6.103515625e-5"),
- INTEL_UNCORE_EVENT_DESC(read.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(write, "event=0xff,umask=0x21"),
- INTEL_UNCORE_EVENT_DESC(write.scale, "6.103515625e-5"),
- INTEL_UNCORE_EVENT_DESC(write.unit, "MiB"),
+ INTEL_UNCORE_FR_EVENT_DESC(read, 0x20, 6.103515625e-5),
+ INTEL_UNCORE_FR_EVENT_DESC(write, 0x21, 6.103515625e-5),
{ /* end: all zeroes */ },
};
@@ -5836,19 +5806,10 @@ static struct freerunning_counters icx_imc_freerunning[] = {
static struct uncore_event_desc icx_uncore_imc_freerunning_events[] = {
INTEL_UNCORE_EVENT_DESC(dclk, "event=0xff,umask=0x10"),
- INTEL_UNCORE_EVENT_DESC(read, "event=0xff,umask=0x20"),
- INTEL_UNCORE_EVENT_DESC(read.scale, "6.103515625e-5"),
- INTEL_UNCORE_EVENT_DESC(read.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(write, "event=0xff,umask=0x21"),
- INTEL_UNCORE_EVENT_DESC(write.scale, "6.103515625e-5"),
- INTEL_UNCORE_EVENT_DESC(write.unit, "MiB"),
-
- INTEL_UNCORE_EVENT_DESC(ddrt_read, "event=0xff,umask=0x30"),
- INTEL_UNCORE_EVENT_DESC(ddrt_read.scale, "6.103515625e-5"),
- INTEL_UNCORE_EVENT_DESC(ddrt_read.unit, "MiB"),
- INTEL_UNCORE_EVENT_DESC(ddrt_write, "event=0xff,umask=0x31"),
- INTEL_UNCORE_EVENT_DESC(ddrt_write.scale, "6.103515625e-5"),
- INTEL_UNCORE_EVENT_DESC(ddrt_write.unit, "MiB"),
+ INTEL_UNCORE_FR_EVENT_DESC(read, 0x20, 6.103515625e-5),
+ INTEL_UNCORE_FR_EVENT_DESC(write, 0x21, 6.103515625e-5),
+ INTEL_UNCORE_FR_EVENT_DESC(ddrt_read, 0x30, 6.103515625e-5),
+ INTEL_UNCORE_FR_EVENT_DESC(ddrt_write, 0x31, 6.103515625e-5),
{ /* end: all zeroes */ },
};
--
2.52.0
next prev parent reply other threads:[~2025-12-31 22:49 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-31 22:42 [PATCH V2 00/13] Add DMR/NVL and missing PTL uncore support Zide Chen
2025-12-31 22:42 ` [PATCH V2 01/13] perf/x86/intel/uncore: Move uncore discovery init struct to header Zide Chen
2026-01-04 1:47 ` Mi, Dapeng
2025-12-31 22:42 ` [PATCH V2 02/13] perf/x86/intel/uncore: Support per-platform discovery base devices Zide Chen
2026-01-04 2:00 ` Mi, Dapeng
2026-01-06 11:01 ` Peter Zijlstra
2025-12-31 22:42 ` [PATCH V2 03/13] perf/x86/intel/uncore: Remove has_generic_discovery_table() Zide Chen
2026-01-04 2:03 ` Mi, Dapeng
2025-12-31 22:42 ` [PATCH V2 04/13] perf/x86/intel/uncore: Add IMH PMON support for Diamond Rapids Zide Chen
2025-12-31 22:42 ` [PATCH V2 05/13] perf/x86/intel/uncore: Add CBB " Zide Chen
2025-12-31 22:42 ` [PATCH V2 06/13] perf/x86/intel/uncore: Add domain global init callback Zide Chen
2026-01-04 2:26 ` Mi, Dapeng
2025-12-31 22:42 ` Zide Chen [this message]
2025-12-31 22:42 ` [PATCH V2 08/13] perf/x86/intel/uncore: Support IIO free-running counters on DMR Zide Chen
2026-01-04 2:31 ` Mi, Dapeng
2026-02-06 0:26 ` Chun-Tse Shao
2026-02-06 5:51 ` Mi, Dapeng
2025-12-31 22:42 ` [PATCH V2 09/13] perf/x86/intel/uncore: Support uncore constraint ranges Zide Chen
2026-01-04 2:36 ` Mi, Dapeng
2025-12-31 22:42 ` [PATCH V2 10/13] perf/x86/intel/uncore: Update DMR uncore constraints preliminarily Zide Chen
2026-01-04 2:41 ` Mi, Dapeng
2025-12-31 22:42 ` [PATCH V2 11/13] perf pmu: Relax uncore wildcard matching to allow numeric suffix Zide Chen
2026-01-21 7:18 ` Ian Rogers
2026-01-21 8:02 ` Mi, Dapeng
2026-01-21 14:33 ` Ian Rogers
2026-01-21 18:19 ` Ian Rogers
2026-01-21 19:03 ` Chen, Zide
2026-01-22 2:09 ` Mi, Dapeng
2026-01-22 7:10 ` Ian Rogers
2026-02-03 23:33 ` Ian Rogers
2026-02-04 21:34 ` Namhyung Kim
2025-12-31 22:42 ` [PATCH V2 12/13] perf/x86/intel/uncore: Add missing PMON units for Panther Lake Zide Chen
2026-01-04 2:48 ` Mi, Dapeng
2026-01-04 2:49 ` Mi, Dapeng
2025-12-31 22:42 ` [PATCH V2 13/13] perf/x86/intel/uncore: Add Nova Lake support Zide Chen
2026-01-04 2:51 ` Mi, Dapeng
2026-01-06 15:08 ` [PATCH V2 00/13] Add DMR/NVL and missing PTL uncore support Peter Zijlstra
2026-01-06 21:19 ` Chen, Zide
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