From: Ian Rogers <irogers@google.com>
To: Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Benjamin Gray <bgray@linux.ibm.com>,
Caleb Biggers <caleb.biggers@intel.com>,
Edward Baker <edward.baker@intel.com>,
Ian Rogers <irogers@google.com>, Ingo Molnar <mingo@redhat.com>,
James Clark <james.clark@linaro.org>,
Jing Zhang <renyu.zj@linux.alibaba.com>,
Jiri Olsa <jolsa@kernel.org>,
John Garry <john.g.garry@oracle.com>, Leo Yan <leo.yan@arm.com>,
Namhyung Kim <namhyung@kernel.org>,
Perry Taylor <perry.taylor@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Samantha Alt <samantha.alt@intel.com>,
Sandipan Das <sandipan.das@amd.com>,
Thomas Falcon <thomas.falcon@intel.com>,
Weilin Wang <weilin.wang@intel.com>, Xu Yang <xu.yang_2@nxp.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org
Subject: [PATCH v10 10/35] perf jevents: Add load store breakdown metrics ldst for AMD
Date: Thu, 8 Jan 2026 11:10:40 -0800 [thread overview]
Message-ID: <20260108191105.695131-11-irogers@google.com> (raw)
In-Reply-To: <20260108191105.695131-1-irogers@google.com>
Give breakdown of number of instructions. Use the counter mask (cmask)
to show the number of cycles taken to retire the instructions.
Reviewed-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/amd_metrics.py | 75 ++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/amd_metrics.py
index d71997177239..b3de74babe40 100755
--- a/tools/perf/pmu-events/amd_metrics.py
+++ b/tools/perf/pmu-events/amd_metrics.py
@@ -280,6 +280,80 @@ def AmdItlb():
], description="Instruction TLB breakdown")
+def AmdLdSt() -> MetricGroup:
+ ldst_ld = Event("ls_dispatch.pure_ld", "ls_dispatch.ld_dispatch")
+ ldst_st = Event("ls_dispatch.pure_st", "ls_dispatch.store_dispatch")
+ ldst_ldc1 = Event(f"{ldst_ld}/cmask=1/")
+ ldst_stc1 = Event(f"{ldst_st}/cmask=1/")
+ ldst_ldc2 = Event(f"{ldst_ld}/cmask=2/")
+ ldst_stc2 = Event(f"{ldst_st}/cmask=2/")
+ ldst_ldc3 = Event(f"{ldst_ld}/cmask=3/")
+ ldst_stc3 = Event(f"{ldst_st}/cmask=3/")
+ ldst_cyc = Event("ls_not_halted_cyc")
+
+ ld_rate = d_ratio(ldst_ld, interval_sec)
+ st_rate = d_ratio(ldst_st, interval_sec)
+
+ ld_v1 = max(ldst_ldc1 - ldst_ldc2, 0)
+ ld_v2 = max(ldst_ldc2 - ldst_ldc3, 0)
+ ld_v3 = ldst_ldc3
+
+ st_v1 = max(ldst_stc1 - ldst_stc2, 0)
+ st_v2 = max(ldst_stc2 - ldst_stc3, 0)
+ st_v3 = ldst_stc3
+
+ return MetricGroup("lpm_ldst", [
+ MetricGroup("lpm_ldst_total", [
+ Metric("lpm_ldst_total_ld", "Number of loads dispatched per second.",
+ ld_rate, "insns/sec"),
+ Metric("lpm_ldst_total_st", "Number of stores dispatched per second.",
+ st_rate, "insns/sec"),
+ ]),
+ MetricGroup("lpm_ldst_percent_insn", [
+ Metric("lpm_ldst_percent_insn_ld",
+ "Load instructions as a percentage of all instructions.",
+ d_ratio(ldst_ld, ins), "100%"),
+ Metric("lpm_ldst_percent_insn_st",
+ "Store instructions as a percentage of all instructions.",
+ d_ratio(ldst_st, ins), "100%"),
+ ]),
+ MetricGroup("lpm_ldst_ret_loads_per_cycle", [
+ Metric(
+ "lpm_ldst_ret_loads_per_cycle_1",
+ "Load instructions retiring in 1 cycle as a percentage of all "
+ "unhalted cycles.", d_ratio(ld_v1, ldst_cyc), "100%"),
+ Metric(
+ "lpm_ldst_ret_loads_per_cycle_2",
+ "Load instructions retiring in 2 cycles as a percentage of all "
+ "unhalted cycles.", d_ratio(ld_v2, ldst_cyc), "100%"),
+ Metric(
+ "lpm_ldst_ret_loads_per_cycle_3",
+ "Load instructions retiring in 3 or more cycles as a percentage"
+ "of all unhalted cycles.", d_ratio(ld_v3, ldst_cyc), "100%"),
+ ]),
+ MetricGroup("lpm_ldst_ret_stores_per_cycle", [
+ Metric(
+ "lpm_ldst_ret_stores_per_cycle_1",
+ "Store instructions retiring in 1 cycle as a percentage of all "
+ "unhalted cycles.", d_ratio(st_v1, ldst_cyc), "100%"),
+ Metric(
+ "lpm_ldst_ret_stores_per_cycle_2",
+ "Store instructions retiring in 2 cycles as a percentage of all "
+ "unhalted cycles.", d_ratio(st_v2, ldst_cyc), "100%"),
+ Metric(
+ "lpm_ldst_ret_stores_per_cycle_3",
+ "Store instructions retiring in 3 or more cycles as a percentage"
+ "of all unhalted cycles.", d_ratio(st_v3, ldst_cyc), "100%"),
+ ]),
+ MetricGroup("lpm_ldst_insn_bt", [
+ Metric("lpm_ldst_insn_bt_ld", "Number of instructions between loads.",
+ d_ratio(ins, ldst_ld), "insns"),
+ Metric("lpm_ldst_insn_bt_st", "Number of instructions between stores.",
+ d_ratio(ins, ldst_st), "insns"),
+ ])
+ ], description="Breakdown of load/store instructions")
+
+
def AmdUpc() -> Metric:
ops = Event("ex_ret_ops", "ex_ret_cops")
upc = d_ratio(ops, smt_cycles)
@@ -366,6 +440,7 @@ def main() -> None:
AmdBr(),
AmdDtlb(),
AmdItlb(),
+ AmdLdSt(),
AmdUpc(),
Idle(),
Rapl(),
--
2.52.0.457.g6b5491de43-goog
next prev parent reply other threads:[~2026-01-08 19:11 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-08 19:10 [PATCH v10 00/35] AMD and Intel metric generation with Python Ian Rogers
2026-01-08 19:10 ` [PATCH v10 01/35] perf jevents: Build support for generating metrics from python Ian Rogers
2026-01-08 19:10 ` [PATCH v10 02/35] perf jevents: Add load event json to verify and allow fallbacks Ian Rogers
2026-01-08 19:10 ` [PATCH v10 03/35] perf jevents: Add RAPL event metric for AMD zen models Ian Rogers
2026-01-08 19:10 ` [PATCH v10 04/35] perf jevents: Add idle " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 05/35] perf jevents: Add upc metric for uops per cycle for AMD Ian Rogers
2026-01-08 19:10 ` [PATCH v10 06/35] perf jevents: Add br metric group for branch statistics on AMD Ian Rogers
2026-01-08 19:10 ` [PATCH v10 07/35] perf jevents: Add itlb metric group for AMD Ian Rogers
2026-01-08 19:10 ` [PATCH v10 08/35] perf jevents: Add dtlb " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 09/35] perf jevents: Add uncore l3 " Ian Rogers
2026-01-08 19:10 ` Ian Rogers [this message]
2026-01-08 19:10 ` [PATCH v10 11/35] perf jevents: Add context switch metrics " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 12/35] perf jevents: Add RAPL metrics for all Intel models Ian Rogers
2026-01-08 19:10 ` [PATCH v10 13/35] perf jevents: Add idle metric for " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 14/35] perf jevents: Add CheckPmu to see if a PMU is in loaded json events Ian Rogers
2026-01-08 19:10 ` [PATCH v10 15/35] perf jevents: Add smi metric group for Intel models Ian Rogers
2026-01-08 19:10 ` [PATCH v10 16/35] perf jevents: Mark metrics with experimental events as experimental Ian Rogers
2026-01-08 19:10 ` [PATCH v10 17/35] perf jevents: Add tsx metric group for Intel models Ian Rogers
2026-01-08 19:10 ` [PATCH v10 18/35] perf jevents: Add br metric group for branch statistics on Intel Ian Rogers
2026-01-08 19:10 ` [PATCH v10 19/35] perf jevents: Add software prefetch (swpf) metric group for Intel Ian Rogers
2026-01-08 19:10 ` [PATCH v10 20/35] perf jevents: Add ports metric group giving utilization on Intel Ian Rogers
2026-01-08 19:10 ` [PATCH v10 21/35] perf jevents: Add L2 metrics for Intel Ian Rogers
2026-01-08 19:10 ` [PATCH v10 22/35] perf jevents: Add load store breakdown metrics ldst " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 23/35] perf jevents: Add ILP metrics " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 24/35] perf jevents: Add context switch " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 25/35] perf jevents: Add FPU " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 26/35] perf jevents: Add Miss Level Parallelism (MLP) metric " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 27/35] perf jevents: Add mem_bw " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 28/35] perf jevents: Add local/remote "mem" breakdown metrics " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 29/35] perf jevents: Add dir " Ian Rogers
2026-01-08 19:11 ` [PATCH v10 30/35] perf jevents: Add C-State metrics from the PCU PMU " Ian Rogers
2026-01-08 19:11 ` [PATCH v10 31/35] perf jevents: Add local/remote miss latency metrics " Ian Rogers
2026-01-08 19:11 ` [PATCH v10 32/35] perf jevents: Add upi_bw metric " Ian Rogers
2026-01-08 19:11 ` [PATCH v10 33/35] perf jevents: Add mesh bandwidth saturation " Ian Rogers
2026-01-08 19:11 ` [PATCH v10 34/35] perf jevents: Add cycles breakdown metric for arm64/AMD/Intel Ian Rogers
2026-01-08 19:11 ` [PATCH v10 35/35] perf jevents: Validate that all names given an Event Ian Rogers
2026-01-20 5:23 ` [PATCH v10 00/35] AMD and Intel metric generation with Python Ian Rogers
2026-01-23 17:12 ` Ian Rogers
2026-01-27 17:07 ` Arnaldo Carvalho de Melo
2026-01-27 18:09 ` Ian Rogers
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260108191105.695131-11-irogers@google.com \
--to=irogers@google.com \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=bgray@linux.ibm.com \
--cc=caleb.biggers@intel.com \
--cc=edward.baker@intel.com \
--cc=james.clark@linaro.org \
--cc=john.g.garry@oracle.com \
--cc=jolsa@kernel.org \
--cc=leo.yan@arm.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=perry.taylor@intel.com \
--cc=peterz@infradead.org \
--cc=renyu.zj@linux.alibaba.com \
--cc=samantha.alt@intel.com \
--cc=sandipan.das@amd.com \
--cc=thomas.falcon@intel.com \
--cc=weilin.wang@intel.com \
--cc=xu.yang_2@nxp.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox