From: Ian Rogers <irogers@google.com>
To: Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Benjamin Gray <bgray@linux.ibm.com>,
Caleb Biggers <caleb.biggers@intel.com>,
Edward Baker <edward.baker@intel.com>,
Ian Rogers <irogers@google.com>, Ingo Molnar <mingo@redhat.com>,
James Clark <james.clark@linaro.org>,
Jing Zhang <renyu.zj@linux.alibaba.com>,
Jiri Olsa <jolsa@kernel.org>,
John Garry <john.g.garry@oracle.com>, Leo Yan <leo.yan@arm.com>,
Namhyung Kim <namhyung@kernel.org>,
Perry Taylor <perry.taylor@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Samantha Alt <samantha.alt@intel.com>,
Sandipan Das <sandipan.das@amd.com>,
Thomas Falcon <thomas.falcon@intel.com>,
Weilin Wang <weilin.wang@intel.com>, Xu Yang <xu.yang_2@nxp.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org
Subject: [PATCH v10 08/35] perf jevents: Add dtlb metric group for AMD
Date: Thu, 8 Jan 2026 11:10:38 -0800 [thread overview]
Message-ID: <20260108191105.695131-9-irogers@google.com> (raw)
In-Reply-To: <20260108191105.695131-1-irogers@google.com>
Add metrics that give an overview and details of the dtlb (zen1, zen2,
zen3).
Reviewed-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/amd_metrics.py | 111 +++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/amd_metrics.py
index 8fb0b55074a2..a4ff88de08b5 100755
--- a/tools/perf/pmu-events/amd_metrics.py
+++ b/tools/perf/pmu-events/amd_metrics.py
@@ -122,6 +122,116 @@ def AmdBr():
description="breakdown of retired branch instructions")
+def AmdDtlb() -> Optional[MetricGroup]:
+ global _zen_model
+ if _zen_model >= 4:
+ return None
+
+ d_dat = Event("ls_dc_accesses") if _zen_model <= 3 else None
+ d_h4k = Event("ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit")
+ d_hcoal = Event(
+ "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit") if _zen_model >= 2 else 0
+ d_h2m = Event("ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit")
+ d_h1g = Event("ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit")
+
+ d_m4k = Event("ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss")
+ d_mcoal = Event(
+ "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss") if _zen_model >= 2 else 0
+ d_m2m = Event("ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss")
+ d_m1g = Event("ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss")
+
+ d_w0 = Event("ls_tablewalker.dc_type0") if _zen_model <= 3 else None
+ d_w1 = Event("ls_tablewalker.dc_type1") if _zen_model <= 3 else None
+ walks = d_w0 + d_w1
+ walks_r = d_ratio(walks, interval_sec)
+ ins_w = d_ratio(ins, walks)
+ l1 = d_dat
+ l1_r = d_ratio(l1, interval_sec)
+ l2_hits = d_h4k + d_hcoal + d_h2m + d_h1g
+ l2_miss = d_m4k + d_mcoal + d_m2m + d_m1g
+ l2_r = d_ratio(l2_hits + l2_miss, interval_sec)
+ l1_miss = l2_hits + l2_miss + walks
+ l1_hits = max(l1 - l1_miss, 0)
+ ins_l = d_ratio(ins, l1_miss)
+
+ return MetricGroup("lpm_dtlb", [
+ MetricGroup("lpm_dtlb_ov", [
+ Metric("lpm_dtlb_ov_insn_bt_l1_miss",
+ "DTLB overview: instructions between l1 misses.", ins_l,
+ "insns"),
+ Metric("lpm_dtlb_ov_insn_bt_walks",
+ "DTLB overview: instructions between dtlb page table walks.",
+ ins_w, "insns"),
+ ]),
+ MetricGroup("lpm_dtlb_l1", [
+ Metric("lpm_dtlb_l1_hits",
+ "DTLB L1 hits as percentage of all DTLB L1 accesses.",
+ d_ratio(l1_hits, l1), "100%"),
+ Metric("lpm_dtlb_l1_miss",
+ "DTLB L1 misses as percentage of all DTLB L1 accesses.",
+ d_ratio(l1_miss, l1), "100%"),
+ Metric("lpm_dtlb_l1_reqs", "DTLB L1 accesses per second.", l1_r,
+ "insns/s"),
+ ]),
+ MetricGroup("lpm_dtlb_l2", [
+ Metric("lpm_dtlb_l2_hits",
+ "DTLB L2 hits as percentage of all DTLB L2 accesses.",
+ d_ratio(l2_hits, l2_hits + l2_miss), "100%"),
+ Metric("lpm_dtlb_l2_miss",
+ "DTLB L2 misses as percentage of all DTLB L2 accesses.",
+ d_ratio(l2_miss, l2_hits + l2_miss), "100%"),
+ Metric("lpm_dtlb_l2_reqs", "DTLB L2 accesses per second.", l2_r,
+ "insns/s"),
+ MetricGroup("lpm_dtlb_l2_4kb", [
+ Metric(
+ "lpm_dtlb_l2_4kb_hits",
+ "DTLB L2 4kb page size hits as percentage of all DTLB L2 4kb "
+ "accesses.", d_ratio(d_h4k, d_h4k + d_m4k), "100%"),
+ Metric(
+ "lpm_dtlb_l2_4kb_miss",
+ "DTLB L2 4kb page size misses as percentage of all DTLB L2 4kb"
+ "accesses.", d_ratio(d_m4k, d_h4k + d_m4k), "100%")
+ ]),
+ MetricGroup("lpm_dtlb_l2_coalesced", [
+ Metric(
+ "lpm_dtlb_l2_coal_hits",
+ "DTLB L2 coalesced page (16kb) hits as percentage of all DTLB "
+ "L2 coalesced accesses.", d_ratio(d_hcoal,
+ d_hcoal + d_mcoal), "100%"),
+ Metric(
+ "lpm_dtlb_l2_coal_miss",
+ "DTLB L2 coalesced page (16kb) misses as percentage of all "
+ "DTLB L2 coalesced accesses.",
+ d_ratio(d_mcoal, d_hcoal + d_mcoal), "100%")
+ ]),
+ MetricGroup("lpm_dtlb_l2_2mb", [
+ Metric(
+ "lpm_dtlb_l2_2mb_hits",
+ "DTLB L2 2mb page size hits as percentage of all DTLB L2 2mb "
+ "accesses.", d_ratio(d_h2m, d_h2m + d_m2m), "100%"),
+ Metric(
+ "lpm_dtlb_l2_2mb_miss",
+ "DTLB L2 2mb page size misses as percentage of all DTLB L2 "
+ "accesses.", d_ratio(d_m2m, d_h2m + d_m2m), "100%")
+ ]),
+ MetricGroup("lpm_dtlb_l2_1g", [
+ Metric(
+ "lpm_dtlb_l2_1g_hits",
+ "DTLB L2 1gb page size hits as percentage of all DTLB L2 1gb "
+ "accesses.", d_ratio(d_h1g, d_h1g + d_m1g), "100%"),
+ Metric(
+ "lpm_dtlb_l2_1g_miss",
+ "DTLB L2 1gb page size misses as percentage of all DTLB L2 "
+ "1gb accesses.", d_ratio(d_m1g, d_h1g + d_m1g), "100%")
+ ]),
+ ]),
+ MetricGroup("lpm_dtlb_walks", [
+ Metric("lpm_dtlb_walks_reqs", "DTLB page table walks per second.",
+ walks_r, "walks/s"),
+ ]),
+ ], description="Data TLB metrics")
+
+
def AmdItlb():
global _zen_model
l2h = Event("bp_l1_tlb_miss_l2_tlb_hit", "bp_l1_tlb_miss_l2_hit")
@@ -236,6 +346,7 @@ def main() -> None:
all_metrics = MetricGroup("", [
AmdBr(),
+ AmdDtlb(),
AmdItlb(),
AmdUpc(),
Idle(),
--
2.52.0.457.g6b5491de43-goog
next prev parent reply other threads:[~2026-01-08 19:11 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-08 19:10 [PATCH v10 00/35] AMD and Intel metric generation with Python Ian Rogers
2026-01-08 19:10 ` [PATCH v10 01/35] perf jevents: Build support for generating metrics from python Ian Rogers
2026-01-08 19:10 ` [PATCH v10 02/35] perf jevents: Add load event json to verify and allow fallbacks Ian Rogers
2026-01-08 19:10 ` [PATCH v10 03/35] perf jevents: Add RAPL event metric for AMD zen models Ian Rogers
2026-01-08 19:10 ` [PATCH v10 04/35] perf jevents: Add idle " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 05/35] perf jevents: Add upc metric for uops per cycle for AMD Ian Rogers
2026-01-08 19:10 ` [PATCH v10 06/35] perf jevents: Add br metric group for branch statistics on AMD Ian Rogers
2026-01-08 19:10 ` [PATCH v10 07/35] perf jevents: Add itlb metric group for AMD Ian Rogers
2026-01-08 19:10 ` Ian Rogers [this message]
2026-01-08 19:10 ` [PATCH v10 09/35] perf jevents: Add uncore l3 " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 10/35] perf jevents: Add load store breakdown metrics ldst " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 11/35] perf jevents: Add context switch metrics " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 12/35] perf jevents: Add RAPL metrics for all Intel models Ian Rogers
2026-01-08 19:10 ` [PATCH v10 13/35] perf jevents: Add idle metric for " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 14/35] perf jevents: Add CheckPmu to see if a PMU is in loaded json events Ian Rogers
2026-01-08 19:10 ` [PATCH v10 15/35] perf jevents: Add smi metric group for Intel models Ian Rogers
2026-01-08 19:10 ` [PATCH v10 16/35] perf jevents: Mark metrics with experimental events as experimental Ian Rogers
2026-01-08 19:10 ` [PATCH v10 17/35] perf jevents: Add tsx metric group for Intel models Ian Rogers
2026-01-08 19:10 ` [PATCH v10 18/35] perf jevents: Add br metric group for branch statistics on Intel Ian Rogers
2026-01-08 19:10 ` [PATCH v10 19/35] perf jevents: Add software prefetch (swpf) metric group for Intel Ian Rogers
2026-01-08 19:10 ` [PATCH v10 20/35] perf jevents: Add ports metric group giving utilization on Intel Ian Rogers
2026-01-08 19:10 ` [PATCH v10 21/35] perf jevents: Add L2 metrics for Intel Ian Rogers
2026-01-08 19:10 ` [PATCH v10 22/35] perf jevents: Add load store breakdown metrics ldst " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 23/35] perf jevents: Add ILP metrics " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 24/35] perf jevents: Add context switch " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 25/35] perf jevents: Add FPU " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 26/35] perf jevents: Add Miss Level Parallelism (MLP) metric " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 27/35] perf jevents: Add mem_bw " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 28/35] perf jevents: Add local/remote "mem" breakdown metrics " Ian Rogers
2026-01-08 19:10 ` [PATCH v10 29/35] perf jevents: Add dir " Ian Rogers
2026-01-08 19:11 ` [PATCH v10 30/35] perf jevents: Add C-State metrics from the PCU PMU " Ian Rogers
2026-01-08 19:11 ` [PATCH v10 31/35] perf jevents: Add local/remote miss latency metrics " Ian Rogers
2026-01-08 19:11 ` [PATCH v10 32/35] perf jevents: Add upi_bw metric " Ian Rogers
2026-01-08 19:11 ` [PATCH v10 33/35] perf jevents: Add mesh bandwidth saturation " Ian Rogers
2026-01-08 19:11 ` [PATCH v10 34/35] perf jevents: Add cycles breakdown metric for arm64/AMD/Intel Ian Rogers
2026-01-08 19:11 ` [PATCH v10 35/35] perf jevents: Validate that all names given an Event Ian Rogers
2026-01-20 5:23 ` [PATCH v10 00/35] AMD and Intel metric generation with Python Ian Rogers
2026-01-23 17:12 ` Ian Rogers
2026-01-27 17:07 ` Arnaldo Carvalho de Melo
2026-01-27 18:09 ` Ian Rogers
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