From: Peter Zijlstra <peterz@infradead.org>
To: Dapeng Mi <dapeng1.mi@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Dapeng Mi <dapeng1.mi@intel.com>, Zide Chen <zide.chen@intel.com>,
Falcon Thomas <thomas.falcon@intel.com>,
Xudong Hao <xudong.hao@intel.com>
Subject: Re: [Patch v2 7/7] perf/x86/intel: Add support for rdpmc user disable feature
Date: Mon, 12 Jan 2026 11:57:38 +0100 [thread overview]
Message-ID: <20260112105738.GG830755@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <20260112051649.1113435-8-dapeng1.mi@linux.intel.com>
On Mon, Jan 12, 2026 at 01:16:49PM +0800, Dapeng Mi wrote:
> +static void intel_pmu_update_rdpmc_user_disable(struct perf_event *event)
> +{
> + /*
> + * Counter scope's user-space rdpmc is disabled by default
> + * except two cases.
> + * a. rdpmc = 2 (user space rdpmc enabled unconditionally)
> + * b. rdpmc = 1 and the event is not a system-wide event.
> + * The count of non-system-wide events would be cleared when
> + * context switches, so no count data is leaked.
> + */
> + if (x86_pmu_has_rdpmc_user_disable(event->pmu)) {
> + if (x86_pmu.attr_rdpmc == X86_USER_RDPMC_ALWAYS_ENABLE ||
> + (x86_pmu.attr_rdpmc == X86_USER_RDPMC_CONDITIONAL_ENABLE &&
> + event->ctx->task))
> + event->hw.config &= ~ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
> + else
> + event->hw.config |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
> + }
> +}
Is it not simpler to invert that condition?
if (x86_pmu.attr_rdpmc == X86_USER_RDPMC_ALWAYS_NEVER ||
!event->ctx->task)
event->hw.config |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
else
event->hw.config &= ~ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
next prev parent reply other threads:[~2026-01-12 10:57 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-12 5:16 [Patch v2 0/7] Enable core PMU for DMR and NVL Dapeng Mi
2026-01-12 5:16 ` [Patch v2 1/7] perf/x86/intel: Support the 4 new OMR MSRs introduced in " Dapeng Mi
2026-01-12 10:27 ` Peter Zijlstra
2026-01-13 1:22 ` Mi, Dapeng
2026-01-12 5:16 ` [Patch v2 2/7] perf/x86/intel: Add support for PEBS memory auxiliary info field in DMR Dapeng Mi
2026-01-12 5:16 ` [Patch v2 3/7] perf/x86/intel: Add core PMU support for DMR Dapeng Mi
2026-01-12 10:41 ` Peter Zijlstra
2026-01-13 1:59 ` Mi, Dapeng
2026-01-12 5:16 ` [Patch v2 4/7] perf/x86/intel: Add support for PEBS memory auxiliary info field in NVL Dapeng Mi
2026-01-12 5:16 ` [Patch v2 5/7] perf/x86/intel: Add core PMU support for Novalake Dapeng Mi
2026-01-12 5:16 ` [Patch v2 6/7] perf/x86: Use macros to replace magic numbers in attr_rdpmc Dapeng Mi
2026-01-12 5:16 ` [Patch v2 7/7] perf/x86/intel: Add support for rdpmc user disable feature Dapeng Mi
2026-01-12 10:57 ` Peter Zijlstra [this message]
2026-01-13 2:29 ` Mi, Dapeng
2026-01-13 10:51 ` Peter Zijlstra
2026-01-13 1:49 ` Ian Rogers
2026-01-13 2:49 ` Mi, Dapeng
2026-03-10 0:04 ` Ian Rogers
2026-03-10 5:28 ` Mi, Dapeng
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