[PATCH] perf symbol: Add RISCV case in get_plt_sizes

[PATCH] perf symbol: Add RISCV case in get_plt_sizes

[cp0613]

From: Chen Pei <cp0613@linux.alibaba.com>

According to RISC-V psABI specification, the PLT (Program Linkage Table)
has the following layout:
- The first PLT entry occupies two 16-byte entries (32 bytes total)
- Subsequent PLT entries take up 16 bytes each

This aligns with the binutils-gdb implementation which defines the same
PLT sizes for RISC-V architecture.

Update get_plt_sizes() to set plt_header_size=32 and plt_entry_size=16
for EM_RISCV, matching the architecture's standard ABI.

Since AARCH64, LOONGARCH, and RISCV have the same PLT size definition,
they are merged together.

Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc
Link: https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=bfd/elfnn-riscv.c

Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
 tools/perf/util/symbol-elf.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c
index 76912c62b6a0..806936d95523 100644
--- a/tools/perf/util/symbol-elf.c
+++ b/tools/perf/util/symbol-elf.c
@@ -372,10 +372,8 @@ static bool get_plt_sizes(struct dso *dso, GElf_Ehdr *ehdr, GElf_Shdr *shdr_plt,
 		*plt_entry_size = 12;
 		return true;
 	case EM_AARCH64:
-		*plt_header_size = 32;
-		*plt_entry_size = 16;
-		return true;
 	case EM_LOONGARCH:
+	case EM_RISCV:
 		*plt_header_size = 32;
 		*plt_entry_size = 16;
 		return true;
-- 
2.50.1

Re: [PATCH] perf symbol: Add RISCV case in get_plt_sizes

[Guo Ren]

On Tue, Mar 17, 2026 at 11:49 AM <cp0613@linux.alibaba.com> wrote:
>
> From: Chen Pei <cp0613@linux.alibaba.com>
>
> According to RISC-V psABI specification, the PLT (Program Linkage Table)
> has the following layout:
> - The first PLT entry occupies two 16-byte entries (32 bytes total)
> - Subsequent PLT entries take up 16 bytes each
>
> This aligns with the binutils-gdb implementation which defines the same
> PLT sizes for RISC-V architecture.
>
> Update get_plt_sizes() to set plt_header_size=32 and plt_entry_size=16
> for EM_RISCV, matching the architecture's standard ABI.
>
> Since AARCH64, LOONGARCH, and RISCV have the same PLT size definition,
> they are merged together.
>
> Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc
> Link: https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=bfd/elfnn-riscv.c

I don't think putting Link here is a good idea. Just copy the part of
the psabi spec v1.0 here:

8.4.6. Program Linkage Table
...
The first entry in the PLT occupies two 16 byte entries:
...
Subsequent function entry stubs in the PLT take up 16 bytes and load a
function pointer from the GOT.

For others:
Reviewed-by: Guo Ren <guoren@kernel.org>


>
>
>
> Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
> ---
>  tools/perf/util/symbol-elf.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c
> index 76912c62b6a0..806936d95523 100644
> --- a/tools/perf/util/symbol-elf.c
> +++ b/tools/perf/util/symbol-elf.c
> @@ -372,10 +372,8 @@ static bool get_plt_sizes(struct dso *dso, GElf_Ehdr *ehdr, GElf_Shdr *shdr_plt,
>                 *plt_entry_size = 12;
>                 return true;
>         case EM_AARCH64:
> -               *plt_header_size = 32;
> -               *plt_entry_size = 16;
> -               return true;
>         case EM_LOONGARCH:
> +       case EM_RISCV:
>                 *plt_header_size = 32;
>                 *plt_entry_size = 16;
>                 return true;
> --
> 2.50.1
>


-- 
Best Regards
 Guo Ren

Re: [PATCH] perf symbol: Add RISCV case in get_plt_sizes

[Namhyung Kim]

On Tue, 17 Mar 2026 11:48:47 +0800, cp0613@linux.alibaba.com wrote:

> According to RISC-V psABI specification, the PLT (Program Linkage Table)
> has the following layout:
> - The first PLT entry occupies two 16-byte entries (32 bytes total)
> - Subsequent PLT entries take up 16 bytes each
> 
> This aligns with the binutils-gdb implementation which defines the same
> PLT sizes for RISC-V architecture.
> 
> [...]

Applied to perf-tools-next, thanks!

Best regards,
Namhyung