From: Geetha sowjanya <gakula@marvell.com>
To: <linux-perf-users@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>
Cc: <mark.rutland@arm.com>, <will@kernel.org>, <krzk+dt@kernel.org>
Subject: [PATCH 0/2] perf: marvell: Add CN20K DDR PMU support
Date: Thu, 26 Mar 2026 14:36:43 +0530 [thread overview]
Message-ID: <20260326090645.22590-1-gakula@marvell.com> (raw)
This series adds support for the Marvell CN20K DRAM Subsystem (DSS)
performance monitor in the existing marvell_cn10k_ddr_pmu driver, and
documents the device tree binding for the new compatible string.
The CN20K PMU provides eight programmable counters and two fixed
counters (DDR reads and writes). Patch 1 adds the devicetree schema for
"marvell,cn20k-ddr-pmu". Patch 2 wires OF and ACPI (MRVL000B) match
entries, adds CN20K register offsets and event maps, and refactors
platform data to use silicon variant flags.
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Geetha sowjanya (2):
dt-bindings: perf: marvell: Document CN20K DDR PMU
perf: marvell: Add CN20K DDR PMU support
.../bindings/perf/marvell-cn20k-ddr.yaml | 37 ++++
drivers/perf/marvell_cn10k_ddr_pmu.c | 186 ++++++++++++++++--
2 files changed, 207 insertions(+), 16 deletions(-)
create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
--
2.25.1
next reply other threads:[~2026-03-26 9:07 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-26 9:06 Geetha sowjanya [this message]
2026-03-26 9:06 ` [PATCH 1/2] dt-bindings: perf: marvell: Document CN20K DDR PMU Geetha sowjanya
2026-03-26 10:33 ` Rob Herring (Arm)
2026-03-26 9:06 ` [PATCH 2/2] perf: marvell: Add CN20K DDR PMU support Geetha sowjanya
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