RE: [EXTERNAL] Re: [PATCH v3 1/2] dt-bindings: perf: marvell: Document CN20K DDR PMU

Geethasowjanya Akula
2026-04-02T09:07:40Z

>-----Original Message-----
>From: Krzysztof Kozlowski <krzk@kernel.org>
>Sent: Thursday, April 2, 2026 12:47 PM
>To: Geethasowjanya Akula <gakula@marvell.com>
>Cc: linux-perf-users@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
>kernel@lists.infradead.org; devicetree@vger.kernel.org;
>mark.rutland@arm.com; will@kernel.org; krzk+dt@kernel.org
>Subject: [EXTERNAL] Re: [PATCH v3 1/2] dt-bindings: perf: marvell: Document
>CN20K DDR PMU
>
>On Wed, Apr 01, 2026 at 01:46:39PM +0530, Geetha sowjanya wrote:
>> Add a devicetree binding for the Marvell CN20K DDR performance monitor
>> block, including the marvell,cn20k-ddr-pmu compatible string and the
>> required MMIO reg region.
>
>You just repeated the diff. No need, we can read the diff, but what we cannot
>read is the hardware you are here describing.
>

Thank you for the review.
You are correct — the commit message and cover letter did not had sufficient
hardware context beyond what is already present in the diff.
CN20K is the successor to CN10K, and the DDR PMU hardware block is functionally
identical to the CN10K DDR PMU, with only minor register offset differences.
This series extends the existing CN10K ddr driver to support CN20K by accounting for those
offset changes.
I will update the commit description to clearly document the DDR PMU hardware,
its relationship to the CN10K implementation.
>>
>> Signed-off-by: Geetha sowjanya <gakula@marvell.com>
>> ---
>> .../bindings/perf/marvell-cn20k-ddr.yaml | 39 +++++++++++++++++++
>
>So you did not test v1. You did not test v2.
>
>Did you finally test this one before sending?
Yes, this version has been validated by running make dt_binding_check
and boot-tested on a CN20K simulator.
>
>> 1 file changed, 39 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
>> b/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
>> new file mode 100644
>> index 000000000000..fa757017d66e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
>> @@ -0,0 +1,39 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
>> +---
>> +$id:
>> +https://urldefense.proofpoint.com/v2/url?u=http-3A__devicetree.org_sc
>> +hemas_perf_marvell-2Dcn20k-2Dddr.yaml-
>23&d=DwIBaQ&c=nKjWec2b6R0mOyPaz
>>
>+7xtfQ&r=UiEt_nUeYFctu7JVLXVlXDhTmq_EAfooaZEYInfGuEQ&m=DMPRMbcsa
>CQDqOv
>> +Hx1f-Oqls-
>X7ZqhI8W9wFel75rh79c2Z0SJ936gMxT4qaMiA5&s=fLAYBOTd64cW4cp0e
>> +b-wxZI6vgY49R2E8M7EUoCk8y4&e=
>> +$schema:
>> +https://urldefense.proofpoint.com/v2/url?u=http-3A__devicetree.org_me
>> +ta-2Dschemas_core.yaml-
>23&d=DwIBaQ&c=nKjWec2b6R0mOyPaz7xtfQ&r=UiEt_nU
>> +eYFctu7JVLXVlXDhTmq_EAfooaZEYInfGuEQ&m=DMPRMbcsaCQDqOvHx1f-
>Oqls-X7Zqh
>> +I8W9wFel75rh79c2Z0SJ936gMxT4qaMiA5&s=VeGgq23L-
>AbFpFxV4e15wgUvn0yEbUDP
>> +xDzNa-1cJ94&e=
>> +
>> +title: Marvell CN20K DDR performance monitor
>> +
>> +description:
>> + Performance Monitoring Unit (PMU) for the DDR controller
>> + in Marvell CN20K SoCs.
>> +
>> +maintainers:
>> + - Geetha sowjanya <gakula@marvell.com>
>> +
>> +properties:
>> + compatible:
>> + const: marvell,cn20k-ddr-pmu
>
>There is no such thing as marvell,cn20k in upstream. What's that?
>
CN20K is the successor to CN10K . Will also re‑check CN20K naming
against existing upstream Marvell SoC compatibles.
>Best regards,
>Krzysztof

Thanks,
Geetha.