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AFNElJ9P80tUEPfza9W4fNtMT/Xuntr6jF/iwefxLrNi2JllNgBuoV2d2+PBslS7RPg1rp89bh87FrM3M7fbS2jI22xK@vger.kernel.org X-Gm-Message-State: AOJu0YyQbqSYQv12KctERxlFvwWZhjMDOJwwFcYT17RDBzv6uGv270IS 6e3Cmq4hyy9Wq2ZkCxtLDRvXIg7hDXhwLB57aQ+pAhJVmcx4OZ/eMQwpsXvDydym547WNnHEa6n dc18TQI4a1A== X-Received: from pgmr35.prod.google.com ([2002:a63:2063:0:b0:c85:735b:ca4a]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:99a9:b0:3a2:d79c:4161 with SMTP id adf61e73a8af0-3b411e8f37amr1437954637.47.1780030361127; Thu, 28 May 2026 21:52:41 -0700 (PDT) Date: Thu, 28 May 2026 21:51:47 -0700 In-Reply-To: <20260529045155.311805-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260529045155.311805-1-irogers@google.com> X-Mailer: git-send-email 2.54.0.823.g6e5bcc1fc9-goog Message-ID: <20260529045155.311805-6-irogers@google.com> Subject: [PATCH v1 05/12] perf vendor events intel: Update emeraldrapids events from 1.21 to 1.23 From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Adrian Hunter , James Clark , "=?UTF-8?q?Andreas=20F=C3=A4rber?=" , Manivannan Sadhasivam , Dapeng Mi , Thomas Falcon , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Ian Rogers Content-Type: text/plain; charset="UTF-8" The updated events and metrics were published in: https://github.com/intel/perfmon/commit/526f1bf0ad6a42d275d1bb115cd337b71c561f92 Signed-off-by: Ian Rogers --- .../arch/x86/emeraldrapids/cache.json | 18 ++++++++++++++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json index b2f8947f6741..ff6071d7728e 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json @@ -181,6 +181,15 @@ "SampleAfterValue": "200003", "UMask": "0xff" }, + { + "BriefDescription": "All requests that hit L2 cache [This event is alias to L2_RQSTS.HIT]", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.HIT", + "PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]", + "SampleAfterValue": "200003", + "UMask": "0xdf" + }, { "BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MISS]", "Counter": "0,1,2,3", @@ -279,6 +288,15 @@ "SampleAfterValue": "200003", "UMask": "0x21" }, + { + "BriefDescription": "All requests that hit L2 cache [This event is alias to L2_REQUEST.HIT]", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.HIT", + "PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]", + "SampleAfterValue": "200003", + "UMask": "0xdf" + }, { "BriefDescription": "L2_RQSTS.HWPF_MISS", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index a52909e212b4..b6d4d37bcf99 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -9,7 +9,7 @@ GenuineIntel-6-4F,v23,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.25,cascadelakex,core GenuineIntel-6-DD,v1.02,clearwaterforest,core GenuineIntel-6-9[6C],v1.05,elkhartlake,core -GenuineIntel-6-CF,v1.21,emeraldrapids,core +GenuineIntel-6-CF,v1.23,emeraldrapids,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-B6,v1.11,grandridge,core -- 2.54.0.823.g6e5bcc1fc9-goog