From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DE1D3B4E98; Fri, 29 May 2026 08:03:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780041830; cv=none; b=tiD49T8nMNuWBDaF78F1NGHMFjV8l3dTMWz69GLSPu9Ea3Q0CmhY169SKijGaikPsROtLltJRJ9OYZPLxPOtwTbg0IGYLa9ExGV7Ud6ckB/m/WEV0Qpkt3/EDpSrDaKpvkxscSgMcyt9O84gFHqAjHrdWjRjwL7THPH7h4T6Gzs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780041830; c=relaxed/simple; bh=CVIk9o8ujVv0PJRRoXST8MXtv56xoAiMpCaH4tgEGnE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LIPGIAj0KpbLIkc3qQAU6oVwrTy0jbUaybLJH2E23pE8vHXJI2a35jah67zumFjBph90NaAynaf6N5hm9SYHNlF5oL8M5/GNCPApvlo8yGAP3QJbcSpZri9ERr9Si+OIQi/js4rB7JM/fzVfSyGu4IA5/b/wI5rKtvefrYBOxiI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=eLvYvP/q; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="eLvYvP/q" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780041829; x=1811577829; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CVIk9o8ujVv0PJRRoXST8MXtv56xoAiMpCaH4tgEGnE=; b=eLvYvP/qt98lYQ8rE4lzf1chWOfkrkmQRObzCEmvCXpJY0OjuxrPGBrA ba1N4YQcTCTeFnZVqnB2b4CjZuYBSrwv/4bHc06xT+BB/kQ3vkMzTZ3bd mlaw6Ah9qCSXWQD4OJVGYOMKbtma7Gy+tkKmR8Uh4bQFPhnkPVTo8o0Tu rRLBx3sXxVNVAVf/1t6n1e358xpenu8gfUgnUOhkQeIk60jmazzpw/idK Cw2BgmY3V1s6b9eD+UVmS/g23D20y67cvQwOuOsQLEB5BpEht4zzWYiyg fUCSgWEn6PtPejRJ282hWuG3Wnb2+lQJYxvbyUNVEqZWa8XzBCn7o1SJC Q==; X-CSE-ConnectionGUID: BzcDAweWQSaF9yZsCsrYgg== X-CSE-MsgGUID: qGDvWAqOSziYPlCkqdM22w== X-IronPort-AV: E=McAfee;i="6800,10657,11800"; a="106342045" X-IronPort-AV: E=Sophos;i="6.24,175,1774335600"; d="scan'208";a="106342045" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2026 01:03:49 -0700 X-CSE-ConnectionGUID: 5TX8Z/CpQK6Dj5D+7loJ5w== X-CSE-MsgGUID: PKXPv8q0Q66hYjxGyBb/4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,175,1774335600"; d="scan'208";a="246802375" Received: from spr.sh.intel.com ([10.112.230.239]) by orviesa003.jf.intel.com with ESMTP; 29 May 2026 01:03:44 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Thomas Gleixner , Dave Hansen , Ian Rogers , Adrian Hunter , Jiri Olsa , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: Mark Rutland , broonie@kernel.org, Ravi Bangoria , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi , Kan Liang Subject: [Patch v8 14/23] perf/x86: Support YMM sampling using sample_simd_vec_reg_* fields Date: Fri, 29 May 2026 15:56:36 +0800 Message-Id: <20260529075645.580362-15-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260529075645.580362-1-dapeng1.mi@linux.intel.com> References: <20260529075645.580362-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This patch introduces support for sampling YMM registers via the sample_simd_vec_reg_* fields. Each YMM register consists of 4 u64 words, assembled from two halves: XMM (the lower 2 u64 words) and YMMH (the upper 2 u64 words). Although both XMM and YMMH data can be retrieved with a single xsaves instruction, they are stored in separate locations. The perf_simd_reg_value() function is responsible for assembling these halves into a complete YMM register for output to userspace. Additionally, sample_simd_vec_reg_qwords should be set to 4 to indicate YMM sampling. Please note YMM sampling is not enabled yet, it will be enabled in a later patch when PERF_PMU_CAP_SIMD_REGS is set. Co-developed-by: Kan Liang Signed-off-by: Kan Liang Signed-off-by: Dapeng Mi --- arch/x86/events/core.c | 8 ++++++++ arch/x86/events/perf_event.h | 9 +++++++++ arch/x86/include/asm/perf_event.h | 4 ++++ arch/x86/include/uapi/asm/perf_regs.h | 6 ++++-- arch/x86/kernel/perf_regs.c | 10 +++++++++- 5 files changed, 34 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 5a4760a1716b..d39710f42ca0 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -732,6 +732,9 @@ int x86_pmu_hw_config(struct perf_event *event) if (event_needs_xmm(event) && !(x86_pmu.ext_regs_mask & XFEATURE_MASK_SSE)) return -EINVAL; + if (event_needs_ymm(event) && + !(x86_pmu.ext_regs_mask & XFEATURE_MASK_YMM)) + return -EINVAL; } } @@ -1776,6 +1779,7 @@ void x86_pmu_clear_perf_regs(struct pt_regs *regs) perf_regs->abi = PERF_SAMPLE_REGS_ABI_NONE; perf_regs->xmm_regs = NULL; + perf_regs->ymmh_regs = NULL; } static void update_perf_regs(struct x86_perf_regs *perf_regs, @@ -1791,6 +1795,8 @@ static void update_perf_regs(struct x86_perf_regs *perf_regs, if (mask & XFEATURE_MASK_SSE) perf_regs->xmm_space = xsave->i387.xmm_space; + if (mask & XFEATURE_MASK_YMM) + perf_regs->ymmh = get_xsave_addr(xsave, XFEATURE_YMM); } /* @@ -1967,6 +1973,8 @@ static void x86_pmu_sample_xregs(struct perf_event *event, if (event_needs_xmm(event)) mask |= XFEATURE_MASK_SSE; + if (event_needs_ymm(event)) + mask |= XFEATURE_MASK_YMM; mask &= x86_pmu.ext_regs_mask; if (sample_type & PERF_SAMPLE_REGS_USER) { diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index b04f5ba3294a..5111eaf8b12a 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -159,6 +159,15 @@ static inline bool event_needs_xmm(struct perf_event *event) return false; } +static inline bool event_needs_ymm(struct perf_event *event) +{ + if (event->attr.sample_simd_regs_enabled && + event->attr.sample_simd_vec_reg_qwords >= PERF_X86_YMM_QWORDS) + return true; + + return false; +} + struct amd_nb { int nb_id; /* NorthBridge id */ int refcnt; /* reference count */ diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index e54d21c13494..1d03b86be65d 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -731,6 +731,10 @@ struct x86_perf_regs { u64 *xmm_regs; u32 *xmm_space; /* for xsaves */ }; + union { + u64 *ymmh_regs; + struct ymmh_struct *ymmh; + }; }; extern unsigned long perf_arch_instruction_pointer(struct pt_regs *regs); diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h index 5b7d5216f0bd..8f513229fbb8 100644 --- a/arch/x86/include/uapi/asm/perf_regs.h +++ b/arch/x86/include/uapi/asm/perf_regs.h @@ -57,7 +57,8 @@ enum perf_event_x86_regs { enum { PERF_X86_SIMD_XMM_REGS = 16, - PERF_X86_SIMD_VEC_REGS_MAX = PERF_X86_SIMD_XMM_REGS, + PERF_X86_SIMD_YMM_REGS = 16, + PERF_X86_SIMD_VEC_REGS_MAX = PERF_X86_SIMD_YMM_REGS, }; #define PERF_X86_SIMD_VEC_MASK __GENMASK_ULL(PERF_X86_SIMD_VEC_REGS_MAX - 1, 0) @@ -65,7 +66,8 @@ enum { enum { /* 1 qword = 8 bytes */ PERF_X86_XMM_QWORDS = 2, - PERF_X86_SIMD_QWORDS_MAX = PERF_X86_XMM_QWORDS, + PERF_X86_YMM_QWORDS = 4, + PERF_X86_SIMD_QWORDS_MAX = PERF_X86_YMM_QWORDS, }; #endif /* _ASM_X86_PERF_REGS_H */ diff --git a/arch/x86/kernel/perf_regs.c b/arch/x86/kernel/perf_regs.c index 7b9b38c189de..9792483360c7 100644 --- a/arch/x86/kernel/perf_regs.c +++ b/arch/x86/kernel/perf_regs.c @@ -77,6 +77,8 @@ u64 perf_reg_value(struct pt_regs *regs, int idx) return regs_get_register(regs, pt_regs_offset[idx]); } +#define PERF_X86_YMMH_QWORDS (PERF_X86_YMM_QWORDS / 2) + u64 perf_simd_reg_value(struct pt_regs *regs, int idx, u16 qwords_idx, bool pred) { @@ -98,6 +100,11 @@ u64 perf_simd_reg_value(struct pt_regs *regs, int idx, return 0; return perf_regs->xmm_regs[idx * PERF_X86_XMM_QWORDS + qwords_idx]; + } else if (qwords_idx < PERF_X86_YMM_QWORDS) { + if (!perf_regs->ymmh_regs) + return 0; + return perf_regs->ymmh_regs[idx * PERF_X86_YMMH_QWORDS + + qwords_idx - PERF_X86_XMM_QWORDS]; } return 0; @@ -121,7 +128,8 @@ int perf_simd_reg_validate(u16 simd_enabled, u16 vec_qwords, if (vec_mask_intr || vec_mask_user) return -EINVAL; } else { - if (vec_qwords != PERF_X86_XMM_QWORDS) + if (vec_qwords != PERF_X86_XMM_QWORDS && + vec_qwords != PERF_X86_YMM_QWORDS) return -EINVAL; if ((!vec_mask_intr && !vec_mask_user) || (vec_mask_intr & ~PERF_X86_SIMD_VEC_MASK) || -- 2.34.1