From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78A573BA222; Fri, 29 May 2026 08:04:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780041852; cv=none; b=WEHi+jaBhcOBfbxCyHvPIwP6wiCILp49a/N8+PVXAWT4y680mZr4XxbYmhWqQsJPjSuNK77uA062YjQhr4zInEXrZjIuyneyaAkRdwkdkF2eWOSpPllDJrY7BuM6cLAr8DKOD14Isd3iLA+vcCHoBI36rImDzz5V/4mTi1O2Mj4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780041852; c=relaxed/simple; bh=lsVhnPtPlS5vmfuMTBFCkTvB3OVqtxoR3bmXqFoTHWU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fnvUB+OWlMbNoEZOLYKOOr4h35EYelqm7MTLZtVM8OELC3AKjPEHy/D0YZt3GY5qU6lUgt0iuJ6z5Mx4Y3INlY0NV6n9ZwP+BeBrWa0j1+vrJQ42zEOSOYXnKIp4yr8pgfP0e7OpTs33bcjLFfXva3AKVOjMc7215dxHhp2USNI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=L0xraY76; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="L0xraY76" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780041849; x=1811577849; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lsVhnPtPlS5vmfuMTBFCkTvB3OVqtxoR3bmXqFoTHWU=; b=L0xraY765b7xFAHqSdDcRgVJsyz+ttRnebT9arQ/9IhHy8K1u6D5d4JB SiaCUlWg4vKololTNz8BxbWxu7bNaGEpA/AZJRZhmDWobx3K8do+YjvRd Su13azVbmZDjqlYq5uj0Blstb1NBkgFeCKWny4UFZO+vMofkd2swekN9z cI4pjbJMg0M6CikWfwjRbqKVUYfbGATNW16jTYRpKi5qRjLVRbnKZA7xW m8/+Nu0H+bPWS0x0BiCEg30F2LKYqj2D5c1Wyn9tmpDfk8BDUq6zCv38s a4EBVQFkqQzBo2r+ke9tX4BlNr82lA4mfXIUlwN/PHZQpi3WjgTOqEfuA Q==; X-CSE-ConnectionGUID: hiltHg68RgqXPaf9Tdvwcw== X-CSE-MsgGUID: foZQkzbjSMu5D+x7xvOSFg== X-IronPort-AV: E=McAfee;i="6800,10657,11800"; a="106342112" X-IronPort-AV: E=Sophos;i="6.24,175,1774335600"; d="scan'208";a="106342112" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2026 01:04:09 -0700 X-CSE-ConnectionGUID: kI/NT3ewSx+qDmfIv2XkEw== X-CSE-MsgGUID: QzLGesZiRSGRbRpEh+hxHg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,175,1774335600"; d="scan'208";a="246802470" Received: from spr.sh.intel.com ([10.112.230.239]) by orviesa003.jf.intel.com with ESMTP; 29 May 2026 01:04:04 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Thomas Gleixner , Dave Hansen , Ian Rogers , Adrian Hunter , Jiri Olsa , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: Mark Rutland , broonie@kernel.org, Ravi Bangoria , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi , Kan Liang Subject: [Patch v8 18/23] perf/x86: Support eGPRs sampling using sample_regs_* fields Date: Fri, 29 May 2026 15:56:40 +0800 Message-Id: <20260529075645.580362-19-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260529075645.580362-1-dapeng1.mi@linux.intel.com> References: <20260529075645.580362-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This patch supports sampling of APX eGPRs (R16 ~ R31) via the sample_regs_* fields. To sample eGPRs, the sample_simd_regs_enabled field must be set. This allows the spare space (reclaimed from the original XMM space) in the sample_regs_* fields to be used for representing eGPRs. The perf_reg_value() function needs to check if the PERF_SAMPLE_REGS_ABI_SIMD flag is set first, and then determine whether to output eGPRs or legacy XMM registers to userspace. The perf_reg_validate() function first checks the simd_enabled argument to determine if the eGPRs bitmap is represented in sample_regs_* fields. It then validates the eGPRs bitmap accordingly. Currently, eGPRs sampling is only supported on the x86_64 architecture, as APX is only available on x86_64 platforms. Please note eGPRs sampling is not enabled yet, it will be enabled in a later patch when PERF_PMU_CAP_SIMD_REGS is set. Suggested-by: Peter Zijlstra (Intel) Co-developed-by: Kan Liang Signed-off-by: Kan Liang Signed-off-by: Dapeng Mi --- arch/x86/events/core.c | 43 ++++++++++++++++++--------- arch/x86/events/intel/core.c | 4 ++- arch/x86/events/perf_event.h | 10 +++++++ arch/x86/include/asm/perf_event.h | 4 +++ arch/x86/include/uapi/asm/perf_regs.h | 26 ++++++++++++++++ arch/x86/kernel/perf_regs.c | 43 ++++++++++++++++----------- 6 files changed, 98 insertions(+), 32 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index d4516d3b5d5a..af874ff3d048 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -708,26 +708,24 @@ int x86_pmu_hw_config(struct perf_event *event) } if (event->attr.sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)) { - /* - * Besides the general purpose registers, XMM registers may - * be collected as well. - */ - if (event_has_extended_regs(event)) { - if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS)) - return -EINVAL; - if (is_sampling_event(event) && !event->attr.precise_ip && - !this_cpu_has(X86_FEATURE_XSAVES)) - return -EINVAL; - if (event->attr.sample_simd_regs_enabled) - return -EINVAL; - } - if (event_has_simd_regs(event)) { + u64 reserved = ~GENMASK_ULL(PERF_REG_MISC_MAX - 1, 0); + if (!(event->pmu->capabilities & PERF_PMU_CAP_SIMD_REGS)) return -EINVAL; if (is_sampling_event(event) && !event->attr.precise_ip && !this_cpu_has(X86_FEATURE_XSAVES)) return -EINVAL; + /* + * The XMM space in the perf_event_x86_regs is reclaimed + * for eGPRs and other general registers. + */ + if ((event->attr.sample_regs_user & reserved) || + (event->attr.sample_regs_intr & reserved)) + return -EINVAL; + if (event_needs_egprs(event) && + !(x86_pmu.ext_regs_mask & XFEATURE_MASK_APX)) + return -EINVAL; /* The vector registers set is not supported */ if (event_needs_xmm(event) && !(x86_pmu.ext_regs_mask & XFEATURE_MASK_SSE)) @@ -744,6 +742,18 @@ int x86_pmu_hw_config(struct perf_event *event) if (event_needs_opmask(event) && !(x86_pmu.ext_regs_mask & XFEATURE_MASK_OPMASK)) return -EINVAL; + } else { + /* + * Besides the general purpose registers, XMM registers may + * be collected as well. + */ + if (event_has_extended_regs(event)) { + if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS)) + return -EINVAL; + if (is_sampling_event(event) && !event->attr.precise_ip && + !this_cpu_has(X86_FEATURE_XSAVES)) + return -EINVAL; + } } } @@ -1792,6 +1802,7 @@ void x86_pmu_clear_perf_regs(struct pt_regs *regs) perf_regs->zmmh_regs = NULL; perf_regs->h16zmm_regs = NULL; perf_regs->opmask_regs = NULL; + perf_regs->egpr_regs = NULL; } static void update_perf_regs(struct x86_perf_regs *perf_regs, @@ -1815,6 +1826,8 @@ static void update_perf_regs(struct x86_perf_regs *perf_regs, perf_regs->h16zmm = get_xsave_addr(xsave, XFEATURE_Hi16_ZMM); if (mask & XFEATURE_MASK_OPMASK) perf_regs->opmask = get_xsave_addr(xsave, XFEATURE_OPMASK); + if (mask & XFEATURE_MASK_APX) + perf_regs->egpr = get_xsave_addr(xsave, XFEATURE_APX); } /* @@ -1999,6 +2012,8 @@ static void x86_pmu_sample_xregs(struct perf_event *event, mask |= XFEATURE_MASK_Hi16_ZMM; if (event_needs_opmask(event)) mask |= XFEATURE_MASK_OPMASK; + if (event_needs_egprs(event)) + mask |= XFEATURE_MASK_APX; mask &= x86_pmu.ext_regs_mask; if (sample_type & PERF_SAMPLE_REGS_USER) { diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 6c06558c416f..a2473f962681 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4698,7 +4698,9 @@ static void intel_pebs_aliases_skl(struct perf_event *event) static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) { unsigned long flags = x86_pmu.large_pebs_flags; - u64 gprs_mask = PEBS_GP_REGS | PERF_REG_EXTENDED_MASK; + u64 gprs_mask = event->attr.sample_simd_regs_enabled ? + PEBS_GP_REGS : + PEBS_GP_REGS | PERF_REG_EXTENDED_MASK; if (event->attr.use_clockid) flags &= ~PERF_SAMPLE_TIME; diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 22b846999cfa..4cc490aa04fc 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -197,6 +197,16 @@ static inline bool event_needs_opmask(struct perf_event *event) return false; } +static inline bool event_needs_egprs(struct perf_event *event) +{ + if (event->attr.sample_simd_regs_enabled && + (event->attr.sample_regs_user & PERF_X86_EGPRS_MASK || + event->attr.sample_regs_intr & PERF_X86_EGPRS_MASK)) + return true; + + return false; +} + struct amd_nb { int nb_id; /* NorthBridge id */ int refcnt; /* reference count */ diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 7e8b60bddd5a..a54ea8fa6a04 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -747,6 +747,10 @@ struct x86_perf_regs { u64 *opmask_regs; struct avx_512_opmask_state *opmask; }; + union { + u64 *egpr_regs; + struct apx_state *egpr; + }; }; extern unsigned long perf_arch_instruction_pointer(struct pt_regs *regs); diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h index 24c981ba8bae..8774a1290fbe 100644 --- a/arch/x86/include/uapi/asm/perf_regs.h +++ b/arch/x86/include/uapi/asm/perf_regs.h @@ -27,9 +27,34 @@ enum perf_event_x86_regs { PERF_REG_X86_R13, PERF_REG_X86_R14, PERF_REG_X86_R15, + /* + * The eGPRs and XMM have overlaps. Only one can be used + * at a time. The ABI PERF_SAMPLE_REGS_ABI_SIMD is used to + * distinguish which one is used. If PERF_SAMPLE_REGS_ABI_SIMD + * is set, then eGPRs is used, otherwise, XMM is used. + * + * Extended GPRs (eGPRs) + */ + PERF_REG_X86_R16, + PERF_REG_X86_R17, + PERF_REG_X86_R18, + PERF_REG_X86_R19, + PERF_REG_X86_R20, + PERF_REG_X86_R21, + PERF_REG_X86_R22, + PERF_REG_X86_R23, + PERF_REG_X86_R24, + PERF_REG_X86_R25, + PERF_REG_X86_R26, + PERF_REG_X86_R27, + PERF_REG_X86_R28, + PERF_REG_X86_R29, + PERF_REG_X86_R30, + PERF_REG_X86_R31, /* These are the limits for the GPRs. */ PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1, PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1, + PERF_REG_MISC_MAX = PERF_REG_X86_R31 + 1, /* These all need two bits set because they are 128bit */ PERF_REG_X86_XMM0 = 32, @@ -54,6 +79,7 @@ enum perf_event_x86_regs { }; #define PERF_REG_EXTENDED_MASK (~((1ULL << PERF_REG_X86_XMM0) - 1)) +#define PERF_X86_EGPRS_MASK __GENMASK_ULL(PERF_REG_X86_R31, PERF_REG_X86_R16) enum { PERF_X86_SIMD_XMM_REGS = 16, diff --git a/arch/x86/kernel/perf_regs.c b/arch/x86/kernel/perf_regs.c index 79803b3b6d6b..006883ad443d 100644 --- a/arch/x86/kernel/perf_regs.c +++ b/arch/x86/kernel/perf_regs.c @@ -61,14 +61,24 @@ u64 perf_reg_value(struct pt_regs *regs, int idx) { struct x86_perf_regs *perf_regs; - if (idx >= PERF_REG_X86_XMM0 && idx < PERF_REG_X86_XMM_MAX) { + if (idx > PERF_REG_X86_R15) { perf_regs = container_of(regs, struct x86_perf_regs, regs); - /* SIMD registers are moved to dedicated sample_simd_vec_reg */ - if (perf_regs->abi & PERF_SAMPLE_REGS_ABI_SIMD) + if (perf_regs->abi == PERF_SAMPLE_REGS_ABI_NONE) return 0; - if (!perf_regs->xmm_regs) - return 0; - return perf_regs->xmm_regs[idx - PERF_REG_X86_XMM0]; + + if (perf_regs->abi & PERF_SAMPLE_REGS_ABI_SIMD) { + if (idx <= PERF_REG_X86_R31) { + if (!perf_regs->egpr_regs) + return 0; + return perf_regs->egpr_regs[idx - PERF_REG_X86_R16]; + } + } else { + if (idx >= PERF_REG_X86_XMM0 && idx < PERF_REG_X86_XMM_MAX) { + if (!perf_regs->xmm_regs) + return 0; + return perf_regs->xmm_regs[idx - PERF_REG_X86_XMM0]; + } + } } if (WARN_ON_ONCE(idx >= ARRAY_SIZE(pt_regs_offset))) @@ -179,18 +189,12 @@ int perf_simd_reg_validate(u16 simd_enabled, u16 vec_qwords, return 0; } -#define PERF_REG_X86_RESERVED (((1ULL << PERF_REG_X86_XMM0) - 1) & \ - ~((1ULL << PERF_REG_X86_MAX) - 1)) +#define PERF_REG_X86_RESERVED (GENMASK_ULL(PERF_REG_X86_XMM0 - 1, PERF_REG_X86_AX) & \ + ~GENMASK_ULL(PERF_REG_X86_R15, PERF_REG_X86_AX)) +#define PERF_REG_X86_EXT_RESERVED (~GENMASK_ULL(PERF_REG_MISC_MAX - 1, PERF_REG_X86_AX)) #ifdef CONFIG_X86_32 -#define REG_NOSUPPORT ((1ULL << PERF_REG_X86_R8) | \ - (1ULL << PERF_REG_X86_R9) | \ - (1ULL << PERF_REG_X86_R10) | \ - (1ULL << PERF_REG_X86_R11) | \ - (1ULL << PERF_REG_X86_R12) | \ - (1ULL << PERF_REG_X86_R13) | \ - (1ULL << PERF_REG_X86_R14) | \ - (1ULL << PERF_REG_X86_R15)) +#define REG_NOSUPPORT GENMASK_ULL(PERF_REG_X86_R15, PERF_REG_X86_R8) int perf_reg_validate(u64 mask, bool simd_enabled) { @@ -214,8 +218,13 @@ u64 perf_reg_abi(struct task_struct *task) int perf_reg_validate(u64 mask, bool simd_enabled) { + if (!simd_enabled && + (!mask || (mask & (REG_NOSUPPORT | PERF_REG_X86_RESERVED)))) + return -EINVAL; + /* The mask could be 0 if only the SIMD registers are interested */ - if (mask & (REG_NOSUPPORT | PERF_REG_X86_RESERVED)) + if (simd_enabled && + (mask & (REG_NOSUPPORT | PERF_REG_X86_EXT_RESERVED))) return -EINVAL; return 0; -- 2.34.1