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Received: from 77-249-17-252.cable.dynamic.v4.ziggo.nl ([77.249.17.252] helo=noisy.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.99.1 #2 (Red Hat Linux)) id 1wSv80-000000060Zr-02Cu; Fri, 29 May 2026 11:11:48 +0000 Received: by noisy.programming.kicks-ass.net (Postfix, from userid 1000) id 73FC030036F; Fri, 29 May 2026 13:11:47 +0200 (CEST) Date: Fri, 29 May 2026 13:11:47 +0200 From: Peter Zijlstra To: Dapeng Mi Cc: Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Thomas Gleixner , Dave Hansen , Ian Rogers , Adrian Hunter , Jiri Olsa , Alexander Shishkin , Andi Kleen , Eranian Stephane , Mark Rutland , broonie@kernel.org, Ravi Bangoria , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao Subject: Re: [Patch v8 01/23] perf/x86/intel: Validate return value of intel_pmu_init_hybrid() Message-ID: <20260529111147.GI3493090@noisy.programming.kicks-ass.net> References: <20260529075645.580362-1-dapeng1.mi@linux.intel.com> <20260529075645.580362-2-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260529075645.580362-2-dapeng1.mi@linux.intel.com> On Fri, May 29, 2026 at 03:56:23PM +0800, Dapeng Mi wrote: > The memory allocation for the x86_pmu.hybrid_pmu[] array in > intel_pmu_init_hybrid() can theoretically fail due to memory shortages. > If this occurs, the initialization of the x86 hybrid PMU would fail. > > Currently, the code does not check the return value of the > intel_pmu_init_hybrid() function, which could lead to attempts to access > the uninitialized x86_pmu.hybrid_pmu[] array, potentially causing a > system panic. > > So, adds a check for the return value of intel_pmu_init_hybrid() to > prevent invalid memory access in such scenarios. > > Signed-off-by: Dapeng Mi > --- > > V8: New patch. > > arch/x86/events/intel/core.c | 29 ++++++++++++++++++++++------- > 1 file changed, 22 insertions(+), 7 deletions(-) > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index 0217e701aeeb..85c329bd52be 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -7870,6 +7870,7 @@ __init int intel_pmu_init(void) > int version, i; > char *name; > struct x86_hybrid_pmu *pmu; > + int ret; > > /* Architectural Perfmon was introduced starting with Core "Yonah" */ > if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { > @@ -8545,7 +8546,9 @@ __init int intel_pmu_init(void) > * > * Initialize the common PerfMon capabilities here. > */ > - intel_pmu_init_hybrid(hybrid_big_small); > + ret = intel_pmu_init_hybrid(hybrid_big_small); > + if (ret < 0) > + return ret; Sashiko notes this will leak the intel_pmu_arch_lbt_init() kmemcache. I'm not entirely sure we care much about that, but its not really nice.