From: sashiko-bot@kernel.org
To: "Dapeng Mi" <dapeng1.mi@linux.intel.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [Patch v8 4/5] perf regs: Enable dumping of SIMD registers
Date: Fri, 29 May 2026 11:23:31 +0000 [thread overview]
Message-ID: <20260529112332.140E61F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260529082451.591783-5-dapeng1.mi@linux.intel.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
New issues:
- [Low] Misleading post-increment of `idx` in `simd_regs_dump__printf` inner loop.
Pre-existing issues:
- [High] Integer underflow in manual `sample_size` calculation in `perf_event__convert_sample_callchain` corrupts the event stream if registers are missing.
--
commit 7e4b22be95dca28326d1271ce91f25c99e231f74
Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
perf regs: Enable dumping of SIMD registers
This patch adds support for dumping SIMD registers using the new
PERF_SAMPLE_REGS_ABI_SIMD ABI.
> diff --git a/tools/perf/builtin-inject.c b/tools/perf/builtin-inject.c
> --- a/tools/perf/builtin-inject.c
> +++ b/tools/perf/builtin-inject.c
> @@ -457,8 +457,13 @@ static int perf_event__convert_sample_callchain(const struct perf_tool *tool,
> /* adjust sample size for stack and regs */
> sample_size -= sample->user_stack.size;
> sample_size -= (hweight64(evsel->core.attr.sample_regs_user) + 1) * sizeof(u64);
[Severity: High]
This is a pre-existing issue, but does unconditionally subtracting the full
expected size of the register mask cause an integer underflow if the perf
sample didn't capture user registers?
If the sample didn't capture user registers (e.g., when sampling a kernel
thread), the ABI is PERF_SAMPLE_REGS_ABI_NONE (0). It seems subtracting the
full mask size would underflow sample_size (a u32), resulting in a massive
size being written to event_copy->header.size.
Could this corrupt the event stream or cause out-of-bounds reads when
perf_event__repipe_synth writes to the pipe?
> - if (sample->user_regs && sample->user_regs->abi & PERF_SAMPLE_REGS_ABI_SIMD)
> - sample_size -= 4 * sizeof(u64); /* Reduce SIMD regs header size */
> + if (sample->user_regs && sample->user_regs->abi & PERF_SAMPLE_REGS_ABI_SIMD) {
> + sample_size -= 4 * sizeof(u64);
> + sample_size -= (sample->user_regs->nr_vectors *
> + sample->user_regs->vector_qwords +
> + sample->user_regs->nr_pred *
> + sample->user_regs->pred_qwords) * sizeof(u64);
> + }
> sample_size += (sample->callchain->nr + 1) * sizeof(u64);
[ ... ]
> diff --git a/tools/perf/util/session.c b/tools/perf/util/session.c
> --- a/tools/perf/util/session.c
> +++ b/tools/perf/util/session.c
[ ... ]
> + for (i = 0; i < regs->nr_vectors; i++) {
> + for (j = 0; j < regs->vector_qwords; j++) {
> + idx = i * regs->vector_qwords + j;
> + if (regs->vector_qwords > 1) {
> + printf(".... %3s[%d][%d] 0x%016" PRIx64 "\n",
> + name, i, j, regs->simd_data[idx++]);
[Severity: Low]
Is the post-increment of idx necessary here?
Since idx is re-initialized at the start of each inner loop iteration
(idx = i * regs->vector_qwords + j), the incremented value seems to be
discarded on the next iteration.
> + } else {
> + printf(".... %3s[%d] 0x%016" PRIx64 "\n",
> + name, i, regs->simd_data[idx++]);
> + }
> + }
> + }
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260529082451.591783-1-dapeng1.mi@linux.intel.com?part=4
next prev parent reply other threads:[~2026-05-29 11:23 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-29 8:24 [Patch v8 0/5] Perf tools: Support eGPRs/SSP/SIMD registers sampling Dapeng Mi
2026-05-29 8:24 ` [Patch v8 1/5] perf headers: Sync perf_event.h/perf_regs.h with the kernel headers Dapeng Mi
2026-05-29 9:23 ` sashiko-bot
2026-05-29 16:59 ` Ian Rogers
2026-05-29 8:24 ` [Patch v8 2/5] perf regs: Support x86 eGPRs/SSP sampling Dapeng Mi
2026-05-29 10:06 ` sashiko-bot
2026-05-29 17:29 ` Ian Rogers
2026-05-29 8:24 ` [Patch v8 3/5] perf regs: Support x86 SIMD registers sampling Dapeng Mi
2026-05-29 10:45 ` sashiko-bot
2026-05-29 17:41 ` Ian Rogers
2026-05-29 8:24 ` [Patch v8 4/5] perf regs: Enable dumping of SIMD registers Dapeng Mi
2026-05-29 11:23 ` sashiko-bot [this message]
2026-05-29 17:45 ` Ian Rogers
2026-05-29 8:24 ` [Patch v8 5/5] perf dwarf-regs: Add SIMD/eGPRs support for x86 DWARF registers Dapeng Mi
2026-05-29 17:56 ` Ian Rogers
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260529112332.140E61F00893@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=dapeng1.mi@linux.intel.com \
--cc=linux-perf-users@vger.kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox