From: sashiko-bot@kernel.org
To: "Zide Chen" <zide.chen@intel.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [PATCH V3 4/7] perf/x86/intel/uncore: Defer ADL global PMON enable to enable_box()
Date: Tue, 02 Jun 2026 16:05:29 +0000 [thread overview]
Message-ID: <20260602160529.8EB701F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260602144908.263680-5-zide.chen@intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The patch defers ADL global PMON enablement to `enable_box()` to save power when no events are in use, but fails to realize that `enable_box()` is unconditionally called by the perf core during event teardown, permanently re-enabling the PMON block after its first use.
--
commit c42f45660bd3d0d4d416922cef01dcc3c1fb5e35
Author: Zide Chen <zide.chen@intel.com>
perf/x86/intel/uncore: Defer ADL global PMON enable to enable_box()
This patch removes adl_uncore_msr_init_box() and defers programming the
global control register to enable_box(). The goal is to reduce power
consumption on Raptor Cove by enabling uncore PMON globally only when a
box is actually used.
Cc: stable@vger.kernel.org
Fixes: 772ed05f3c5c ("perf/x86/intel/uncore: Add Alder Lake support")
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
> diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c
> index 3dbc6bacbd9de..edddd4f9ab5fc 100644
> --- a/arch/x86/events/intel/uncore_snb.c
> +++ b/arch/x86/events/intel/uncore_snb.c
[ ... ]
> @@ -563,12 +563,6 @@ void tgl_uncore_cpu_init(void)
> skl_uncore_msr_ops.init_box = rkl_uncore_msr_init_box;
> }
>
> -static void adl_uncore_msr_init_box(struct intel_uncore_box *box)
> -{
> - if (box->pmu->pmu_idx == 0)
> - wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);
> -}
> -
> static void adl_uncore_msr_enable_box(struct intel_uncore_box *box)
> {
> wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);
> }
[Severity: Medium]
Will this leave the PMU permanently enabled after its first use?
During event teardown, the perf core brackets the removal with calls to
perf_pmu_disable() and perf_pmu_enable(). perf_pmu_enable() will ultimately
invoke uncore_pmu_enable(), which unconditionally calls enable_box().
Because adl_uncore_msr_enable_box() unconditionally writes the enable bit
without checking if there are any remaining active events (for example,
checking if box->n_active > 0), the global MSR appears to be immediately
re-enabled at the end of the teardown process.
Does this mean the intended power savings are lost the first time the
PMU is used?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260602144908.263680-1-zide.chen@intel.com?part=4
next prev parent reply other threads:[~2026-06-02 16:05 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-02 14:49 [PATCH V3 0/7] perf/x86/intel/uncore: Bug fixes and cleanups Zide Chen
2026-06-02 14:49 ` [PATCH V3 1/7] perf/x86/intel/uncore: Fix discovery unit lookup for multi-die systems Zide Chen
2026-06-02 15:22 ` sashiko-bot
2026-06-02 14:49 ` [PATCH V3 2/7] perf/x86/intel/uncore: Guard against invalid box control address Zide Chen
2026-06-02 15:39 ` sashiko-bot
2026-06-02 14:49 ` [PATCH V3 3/7] perf/x86/intel/uncore: Fix PCI device refcount leak in UPI discovery Zide Chen
2026-06-02 14:49 ` [PATCH V3 4/7] perf/x86/intel/uncore: Defer ADL global PMON enable to enable_box() Zide Chen
2026-06-02 16:05 ` sashiko-bot [this message]
2026-06-02 14:49 ` [PATCH V3 5/7] perf/x86/intel/uncore: Move die_to_cpu() to uncore.c Zide Chen
2026-06-02 14:49 ` [PATCH V3 6/7] perf/x86/intel/uncore: Fix uncore_die_to_cpu() for offline dies Zide Chen
2026-06-02 14:49 ` [PATCH V3 7/7] perf/x86/intel/uncore: Implement global init callback for GNR uncore Zide Chen
2026-06-02 16:44 ` sashiko-bot
2026-06-03 2:48 ` [PATCH V3 0/7] perf/x86/intel/uncore: Bug fixes and cleanups Mi, Dapeng
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