From: sashiko-bot@kernel.org
To: "Atish Patra" <atish.patra@linux.dev>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org,
linux-perf-users@vger.kernel.org
Subject: Re: [PATCH v6 20/21] TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing
Date: Tue, 09 Jun 2026 06:17:49 +0000 [thread overview]
Message-ID: <20260609061750.2FBCE1F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260608-counter_delegation-v6-20-285b72ed65a9@meta.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The patch adds synthetic test events explicitly marked 'TEST(do-not-upstream)' to the production RISC-V SBI PMU driver, polluting the UAPI.
--
commit 286ddcbf491d3a026da1733168d9b7d29bcd2fbe
Author: Atish Patra <atishp@meta.com>
TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing
This commit adds fake performance monitoring events to test counter delegation
and counter-mask constraints in Qemu. The events use codes that Qemu does not
model to verify allocation and programming behavior.
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 74acac54328e0..3c0829c0a42ab 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
[ ... ]
> @@ -483,6 +489,9 @@ static struct attribute *qemu_virt_event_group[] = {
> RVPMU_EVENT_ATTR_PTR(dTLB_load_miss),
> RVPMU_EVENT_ATTR_PTR(dTLB_store_miss),
> RVPMU_EVENT_ATTR_PTR(iTLB_load_miss),
> + RVPMU_EVENT_ATTR_PTR(fake_any),
> + RVPMU_EVENT_ATTR_PTR(fake_ctr3),
> + RVPMU_EVENT_ATTR_PTR(fake_ctr34),
[Severity: Medium]
Does this code introduce a regression by exposing test functionality?
This patch is explicitly marked "do-not-upstream" and unconditionally adds
synthetic test events to the exposed Qemu platform pmu events array in
qemu_virt_event_group[].
Exposing these fake hardware events (fake-any, fake-ctr3, fake-ctr34)
to userspace pollutes the production sysfs uapi. These will appear in
perf list and could confuse users or automated tools.
> NULL,
> };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260608-counter_delegation-v6-0-285b72ed65a9@meta.com?part=20
next prev parent reply other threads:[~2026-06-09 6:17 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-09 6:01 [PATCH v6 00/21] Add Counter delegation ISA extension support Atish Patra
2026-06-09 6:01 ` [PATCH v6 01/21] RISC-V: Add Sxcsrind ISA extension CSR definitions Atish Patra
2026-06-09 6:01 ` [PATCH v6 02/21] RISC-V: Add Sxcsrind ISA extension definition and parsing Atish Patra
2026-06-09 6:01 ` [PATCH v6 03/21] dt-bindings: riscv: add Sxcsrind ISA extension description Atish Patra
2026-06-09 6:09 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 04/21] RISC-V: Define indirect CSR access helpers Atish Patra
2026-06-09 6:15 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 05/21] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2026-06-09 6:01 ` [PATCH v6 06/21] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2026-06-09 6:09 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 07/21] RISC-V: Add Sscfg extension CSR definition Atish Patra
2026-06-09 6:01 ` [PATCH v6 08/21] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing Atish Patra
2026-06-09 6:14 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 09/21] dt-bindings: riscv: add Counter delegation ISA extensions description Atish Patra
2026-06-09 6:12 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 10/21] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2026-06-09 6:18 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 11/21] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2026-06-09 6:17 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 12/21] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2026-06-09 6:16 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 13/21] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2026-06-09 6:23 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 14/21] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2026-06-09 6:33 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 15/21] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2026-06-09 6:23 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 16/21] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2026-06-09 6:21 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 17/21] RISC-V: perf: Add Qemu virt machine events Atish Patra
2026-06-09 6:22 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 18/21] tools/perf: Support event code for arch standard events Atish Patra
2026-06-09 6:18 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 19/21] tools/perf: Add RISC-V CounterIDMask event field Atish Patra
2026-06-09 6:01 ` [PATCH v6 20/21] TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing Atish Patra
2026-06-09 6:17 ` sashiko-bot [this message]
2026-06-09 6:01 ` [PATCH v6 21/21] TEST(do-not-upstream): fake qemu vendor JSON + mapfile entry for CounterIDMask path Atish Patra
2026-06-09 6:20 ` sashiko-bot
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