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From: Peter Zijlstra <peterz@infradead.org>
To: Dapeng Mi <dapeng1.mi@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	Eranian Stephane <eranian@google.com>,
	linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	Dapeng Mi <dapeng1.mi@intel.com>, Zide Chen <zide.chen@intel.com>,
	Falcon Thomas <thomas.falcon@intel.com>,
	Xudong Hao <xudong.hao@intel.com>
Subject: Re: [Patch v2 4/9] perf/x86/intel: Fallback to sw branch type decoding if no hw decoding
Date: Tue, 9 Jun 2026 16:49:34 +0200	[thread overview]
Message-ID: <20260609144934.GC49951@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <20260609050222.2458129-5-dapeng1.mi@linux.intel.com>

On Tue, Jun 09, 2026 at 01:02:17PM +0800, Dapeng Mi wrote:
> intel_pmu_lbr_filter() currently assumes Arch LBR provides hardware
> branch-type decoding and skips software decoding on that path.
> 
> However, Arch LBR may not always expose branch-type information. In
> that case, treating entries as hardware-decoded can misclassify sampled
> branches (for example, defaulting to JCC), which breaks branch-type
> filtering results.
> 
> Fix this by using software branch-type decoding when hardware
> branch-type decoding is unavailable (that is, when x86_lbr_type is not
> enabled). This keeps branch classification and filtering behavior
> correct across Arch LBR configurations.
> 
> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
> ---
>  arch/x86/events/intel/lbr.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
> index 72f2adcda7c6..d4c0ed85e1fb 100644
> --- a/arch/x86/events/intel/lbr.c
> +++ b/arch/x86/events/intel/lbr.c
> @@ -1232,6 +1232,7 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
>  		 * OTHER_BRANCH branch type still rely on software decoding.
>  		 */
>  		if (static_cpu_has(X86_FEATURE_ARCH_LBR) &&
> +		    static_branch_likely(&x86_lbr_type) &&
>  		    type <= ARCH_LBR_BR_TYPE_KNOWN_MAX) {
>  			to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
>  			type = arch_lbr_br_type_map[type] | to_plm;

Now you have two static branches in concert. Best to make sure
x86_lbr_type covers both conditions, no?

  parent reply	other threads:[~2026-06-09 14:49 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-09  5:02 [Patch v2 0/9] perf/x86: Miscellaneous PMU bug fixes Dapeng Mi
2026-06-09  5:02 ` [Patch v2 1/9] perf/x86/intel: Remove anythread_deprecated bit from perf_capabilities Dapeng Mi
2026-06-09  5:02 ` [Patch v2 2/9] perf/x86: Introduce is_x86_pmu() helper Dapeng Mi
2026-06-09  5:02 ` [Patch v2 3/9] perf/x86: Update cap_user_rdpmc base on rdpmc user disable state Dapeng Mi
2026-06-09 14:48   ` Peter Zijlstra
2026-06-09  5:02 ` [Patch v2 4/9] perf/x86/intel: Fallback to sw branch type decoding if no hw decoding Dapeng Mi
2026-06-09  5:24   ` sashiko-bot
2026-06-09 10:04     ` Mi, Dapeng
2026-06-09 14:49   ` Peter Zijlstra [this message]
2026-06-09  5:02 ` [Patch v2 5/9] perf/x86/intel: Drop LBR entries whose privilege level mismatches br_sel Dapeng Mi
2026-06-09  5:21   ` sashiko-bot
2026-06-09  9:40     ` Mi, Dapeng
2026-06-09 14:52   ` Peter Zijlstra
2026-06-09  5:02 ` [Patch v2 6/9] perf/x86/intel: Validate return value of intel_pmu_init_hybrid() Dapeng Mi
2026-06-09  5:25   ` sashiko-bot
2026-06-09  9:44     ` Mi, Dapeng
2026-06-09  5:02 ` [Patch v2 7/9] perf/x86/intel: Drop fixed-counter PEBS constraints for baseline PEBS Dapeng Mi
2026-06-09  5:02 ` [Patch v2 8/9] perf/core: Fix kernel register info leak via hardware skid Dapeng Mi
2026-06-09  5:02 ` [Patch v2 9/9] perf/core: Check kernel access when kernel callchains are requested Dapeng Mi
2026-06-09  5:24   ` sashiko-bot
2026-06-09  9:49     ` Mi, Dapeng

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