From: sashiko-bot@kernel.org
To: "Dapeng Mi" <dapeng1.mi@linux.intel.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [Patch v3 5/8] perf/x86/intel: Validate the return value of intel_pmu_init_hybrid()
Date: Fri, 12 Jun 2026 09:31:19 +0000 [thread overview]
Message-ID: <20260612093119.7FA3E1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260612090114.3188886-6-dapeng1.mi@linux.intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Relocating `intel_pmu_arch_lbr_init()` below `intel_pmu_check_event_constraints_all()` bypasses the dynamic constraint validation for branch counters.
--
commit 4ceb25a65fdf63fe8fa33e932139cf0a5d28e924
Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
perf/x86/intel: Validate the return value of intel_pmu_init_hybrid()
This patch validates the return value of intel_pmu_init_hybrid() to avoid a
null-pointer dereference. It also defers intel_pmu_arch_lbr_init() until after
hybrid PMU initialization succeeds to avoid destroying the kmem cache on
failure.
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index db52e7e53a6cd..74dbf24b0ab63 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
[ ... ]
> @@ -8829,6 +8842,9 @@ __init int intel_pmu_init(void)
>
> intel_pmu_check_event_constraints_all(NULL);
>
> + if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
> + intel_pmu_arch_lbr_init();
> +
[Severity: Medium]
Does moving intel_pmu_arch_lbr_init() below
intel_pmu_check_event_constraints_all() bypass the dynamic constraint
validation for branch counters?
When intel_pmu_check_event_constraints_all() runs, it eventually calls
intel_pmu_check_dyn_constr(). This check relies on the PMU_FL_BR_CNTR flag
and the x86_pmu.lbr_counters mask:
arch/x86/events/intel/core.c:intel_pmu_check_dyn_constr() {
...
case DYN_CONSTR_BR_CNTR:
if (x86_pmu.flags & PMU_FL_BR_CNTR)
mask = x86_pmu.lbr_counters;
break;
...
}
Because intel_pmu_arch_lbr_init() is now deferred until after this validation,
the PMU_FL_BR_CNTR flag hasn't been set yet. Will this cause the dynamic
constraint check for branch counters to evaluate to false and be skipped?
> /*
> * Access LBR MSR may cause #GP under certain circumstances.
> * Check all LBR MSR here.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260612090114.3188886-1-dapeng1.mi@linux.intel.com?part=5
next prev parent reply other threads:[~2026-06-12 9:31 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-12 9:01 [Patch v3 0/8] perf/x86: Miscellaneous PMU bug fixes Dapeng Mi
2026-06-12 9:01 ` [Patch v3 1/8] perf/x86/intel: Remove anythread_deprecated bit from perf_capabilities Dapeng Mi
2026-06-12 9:46 ` Peter Zijlstra
2026-06-12 9:01 ` [Patch v3 2/8] perf/x86/intel: Keep cap_user_rdpmc in sync with RDPMC user-disable state Dapeng Mi
2026-06-12 9:01 ` [Patch v3 3/8] perf/x86/intel: Fallback to sw branch type decoding if no hw decoding Dapeng Mi
2026-06-12 9:21 ` sashiko-bot
2026-06-12 9:01 ` [Patch v3 4/8] perf/x86/intel: Fix kernel address leakages in LBR stack Dapeng Mi
2026-06-12 9:18 ` sashiko-bot
2026-06-12 9:01 ` [Patch v3 5/8] perf/x86/intel: Validate the return value of intel_pmu_init_hybrid() Dapeng Mi
2026-06-12 9:31 ` sashiko-bot [this message]
2026-06-12 9:01 ` [Patch v3 6/8] perf/x86/intel: Drop fixed-counter PEBS constraints for baseline PEBS Dapeng Mi
2026-06-12 9:01 ` [Patch v3 7/8] perf/core: Fix kernel register info leak via hardware skid Dapeng Mi
2026-06-12 9:01 ` [Patch v3 8/8] perf/core: Check kernel access when kernel callchains are requested Dapeng Mi
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