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From: sashiko-bot@kernel.org
To: "Atish Patra" <atish.patra@linux.dev>
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org,
	linux-perf-users@vger.kernel.org, robh@kernel.org
Subject: Re: [PATCH v7 21/22] TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing
Date: Mon, 22 Jun 2026 08:32:43 +0000	[thread overview]
Message-ID: <20260622083244.545201F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260622-counter_delegation-v7-21-0ba2fd34614e@meta.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The patch introduces fake PMU events intended solely for testing and unconditionally pollutes the production sysfs ABI.
--

commit 4ceddd2e5a59573074b3f2f8f712ad1f99946ae0
Author: Atish Patra <atishp@meta.com>

TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing

This commit adds fake PMU event codes to exercise counter-delegation allocation
and counter-mask constraints in QEMU. It unconditionally exposes these test
events to the user by adding them to the driver's event group.

> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 3cb7a1f4035ef..13a9f1fe42936 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c

[ ... ]

> @@ -499,6 +505,9 @@ static struct attribute *qemu_virt_event_group[] = {
>  	RVPMU_EVENT_ATTR_PTR(dTLB_load_miss),
>  	RVPMU_EVENT_ATTR_PTR(dTLB_store_miss),
>  	RVPMU_EVENT_ATTR_PTR(iTLB_load_miss),
> +	RVPMU_EVENT_ATTR_PTR(fake_any),
> +	RVPMU_EVENT_ATTR_PTR(fake_ctr3),
> +	RVPMU_EVENT_ATTR_PTR(fake_ctr34),

[Severity: Medium]
Is it intended to leave these test-only events unconditionally exposed in the
production sysfs ABI?

Although the patch is explicitly marked as do-not-upstream, these fake events
are added directly to qemu_virt_event_group without being cleaned up later in
the series. This will visibly alter userspace tools like perf list on standard
RISC-V virtual workloads.

Could these test artifacts be separated from the mainline driver or removed
entirely if this series is routed upstream?

>  	NULL,
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260622-counter_delegation-v7-0-0ba2fd34614e@meta.com?part=21

  reply	other threads:[~2026-06-22  8:32 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-22  8:04 [PATCH v7 00/22] Add Counter delegation ISA extension support Atish Patra
2026-06-22  8:04 ` [PATCH v7 01/22] RISC-V: perf: fix resource cleanup on driver probe failure Atish Patra
2026-06-22  8:24   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 02/22] RISC-V: Add Sxcsrind ISA extension CSR definitions Atish Patra
2026-06-22  8:04 ` [PATCH v7 03/22] RISC-V: Add Sxcsrind ISA extension definition and parsing Atish Patra
2026-06-22  8:04 ` [PATCH v7 04/22] dt-bindings: riscv: add Sxcsrind ISA extension description Atish Patra
2026-06-22  8:04 ` [PATCH v7 05/22] RISC-V: Define indirect CSR access helpers Atish Patra
2026-06-22  8:17   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 06/22] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2026-06-22  8:17   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 07/22] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2026-06-22  8:04 ` [PATCH v7 08/22] RISC-V: Add Sscfg extension CSR definition Atish Patra
2026-06-22  8:04 ` [PATCH v7 09/22] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing Atish Patra
2026-06-22  8:18   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 10/22] dt-bindings: riscv: add Counter delegation ISA extensions description Atish Patra
2026-06-22  8:20   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 11/22] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2026-06-22  8:04 ` [PATCH v7 12/22] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2026-06-22  8:24   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 13/22] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2026-06-22  8:04 ` [PATCH v7 14/22] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2026-06-22  8:33   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 15/22] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2026-06-22  8:04 ` [PATCH v7 16/22] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2026-06-22  8:30   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 17/22] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2026-06-22  8:04 ` [PATCH v7 18/22] RISC-V: perf: Add Qemu virt machine events Atish Patra
2026-06-22  8:39   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 19/22] tools/perf: Support event code for arch standard events Atish Patra
2026-06-22  8:34   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 20/22] tools/perf: Add RISC-V CounterIDMask event field Atish Patra
2026-06-22  8:04 ` [PATCH v7 21/22] TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing Atish Patra
2026-06-22  8:32   ` sashiko-bot [this message]
2026-06-22  8:04 ` [PATCH v7 22/22] TEST(do-not-upstream): fake qemu vendor JSON + mapfile entry for CounterIDMask path Atish Patra
2026-06-22  8:35   ` sashiko-bot

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