From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D15B4361667; Mon, 6 Jul 2026 02:02:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783303351; cv=none; b=WeB3xTT/tVB52CCg65XTUftGlMuIMBOBCPzj5w8LZkXeFYdSyxFRanu6jBgEz5r5aB2p3YsesnEOJ3kdZeOFtgIfYycP1OOMCEfsMe1PQ71stqJ49vzK1dPKbbm1OEVzsvNBbblyu0tMRf/STXD5HjaQ3MLLGe7klSOqt8ZlWN8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783303351; c=relaxed/simple; bh=NbBGKmVAt5jKKrT4MDSt+WWPPIbXR8UjyBphCL2N9dM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=r13Mt0abSduTWEgIWxPg+ehHFHVZIhxnCm2OoGtDww16Oy+bLm7j6SL1xaSRDbORYvxtNIlK+15rEZLDWeFlzID6wWTn5gFb8cfvyp95a+K85OQYaIxEGurspclFwvQGNTQsaAKR7Gap96bu1BUm3ymCRWgsIUYmLlnMqBil+DU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bKfKqgQq; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bKfKqgQq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1783303350; x=1814839350; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NbBGKmVAt5jKKrT4MDSt+WWPPIbXR8UjyBphCL2N9dM=; b=bKfKqgQqHlp5DnPeRq68gNGV3ITcxRFs2LSVvZlhe+oL2SKVOsScSZYb xXgRt7pJ2euKTiO4mz68vl+PWyUFnK5+dBzyd4pBKBOUSFlh985J1z2oa 9QtMCABGz37dXjj244zjcmLH18AbGWjYeCe4qyoMIzSIoWN14h9Cty/Ix m2Sxb+JHAVkMhLCLauRQohZGWkP18aOkZqmxzmwternAh67cmb0bcdlt7 avYWfx4WSgfLwKk6o30G6q/1+u+iIQaFt9fKhL7sO02pYOlsxLktgoi3f M8pQoxb54597p2vKPVpR6Yyl9oMUw0JGNXhHk9sWeYv6kT+0o1k32Q4Qe A==; X-CSE-ConnectionGUID: vrRtVa8JSOS6eJwxRPyWfg== X-CSE-MsgGUID: Q0UHIDLWSdqqYQ14V/greA== X-IronPort-AV: E=McAfee;i="6800,10657,11838"; a="83911712" X-IronPort-AV: E=Sophos;i="6.25,149,1779174000"; d="scan'208";a="83911712" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2026 19:02:30 -0700 X-CSE-ConnectionGUID: GVcyNaMzReuIlig9YrVwPA== X-CSE-MsgGUID: tEFCnvfjQpKsZU0wiGHJjg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,149,1779174000"; d="scan'208";a="247191451" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa009.fm.intel.com with ESMTP; 05 Jul 2026 19:02:24 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Thomas Gleixner , Dave Hansen , Ian Rogers , Adrian Hunter , Jiri Olsa , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: Mark Rutland , broonie@kernel.org, Ravi Bangoria , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi , Kan Liang Subject: [Patch v9 16/24] perf/x86: Support ZMM sampling using sample_simd_vec_reg_* fields Date: Mon, 6 Jul 2026 09:54:31 +0800 Message-Id: <20260706015439.3040804-17-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260706015439.3040804-1-dapeng1.mi@linux.intel.com> References: <20260706015439.3040804-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Support sampling of ZMM registers via the sample_simd_vec_reg_* fields. Each ZMM register consists of 8 u64 words. Current x86 hardware supports up to 32 ZMM registers. For ZMM registers from ZMM0 to ZMM15, they are assembled from three parts: XMM (the lower 2 u64 words), YMMH (the middle 2 u64 words), and ZMMH (the upper 4 u64 words). The perf_simd_reg_value() function is responsible for assembling these three parts into a complete ZMM register for output to userspace. For ZMM registers ZMM16 to ZMM31, each register can be read as a whole and directly outputted to userspace. Additionally, sample_simd_vec_reg_qwords should be set to 8 to indicate ZMM sampling. ZMM sampling will be enabled in a subsequent patch that sets PERF_PMU_CAP_SIMD_REGS. Co-developed-by: Kan Liang Signed-off-by: Kan Liang Signed-off-by: Dapeng Mi --- arch/x86/events/core.c | 16 +++++++++++++ arch/x86/events/perf_event.h | 33 +++++++++++++++++++++++++++ arch/x86/include/asm/perf_event.h | 8 +++++++ arch/x86/include/uapi/asm/perf_regs.h | 8 +++++-- arch/x86/kernel/perf_regs.c | 16 ++++++++++++- 5 files changed, 78 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 10d90050def3..ef0e238a4678 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -729,6 +729,12 @@ int x86_pmu_hw_config(struct perf_event *event) if (event_needs_ymm(event) && !(x86_pmu.ext_regs_mask & XFEATURE_MASK_YMM)) return -EINVAL; + if (event_needs_low16_zmm(event) && + !(x86_pmu.ext_regs_mask & XFEATURE_MASK_ZMM_Hi256)) + return -EINVAL; + if (event_needs_high16_zmm(event) && + !(x86_pmu.ext_regs_mask & XFEATURE_MASK_Hi16_ZMM)) + return -EINVAL; } } @@ -1774,6 +1780,8 @@ void x86_pmu_clear_perf_regs(struct pt_regs *regs) perf_regs->abi = PERF_SAMPLE_REGS_ABI_NONE; perf_regs->xmm_regs = NULL; perf_regs->ymmh_regs = NULL; + perf_regs->zmmh_regs = NULL; + perf_regs->h16zmm_regs = NULL; } static void update_perf_regs(struct x86_perf_regs *perf_regs, @@ -1791,6 +1799,10 @@ static void update_perf_regs(struct x86_perf_regs *perf_regs, perf_regs->xmm_space = xsave->i387.xmm_space; if (mask & XFEATURE_MASK_YMM) perf_regs->ymmh = get_xsave_addr(xsave, XFEATURE_YMM); + if (mask & XFEATURE_MASK_ZMM_Hi256) + perf_regs->zmmh = get_xsave_addr(xsave, XFEATURE_ZMM_Hi256); + if (mask & XFEATURE_MASK_Hi16_ZMM) + perf_regs->h16zmm = get_xsave_addr(xsave, XFEATURE_Hi16_ZMM); } /* @@ -1984,6 +1996,10 @@ static void x86_pmu_sample_xregs(struct perf_event *event, mask |= XFEATURE_MASK_SSE; if (event_needs_ymm(event)) mask |= XFEATURE_MASK_YMM; + if (event_needs_low16_zmm(event)) + mask |= XFEATURE_MASK_ZMM_Hi256; + if (event_needs_high16_zmm(event)) + mask |= XFEATURE_MASK_Hi16_ZMM; mask &= x86_pmu.ext_regs_mask; if ((sample_type & PERF_SAMPLE_REGS_USER) && data->regs_user.regs) { diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 13f1f34ff8b0..01414b3a88fd 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -176,6 +176,39 @@ static inline bool event_needs_ymm(struct perf_event *event) return false; } +static inline bool event_needs_low16_zmm(struct perf_event *event) +{ + if (!(event->attr.sample_type & + (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER))) + return false; + + if (event->attr.sample_simd_regs_enabled && + event->attr.sample_simd_vec_reg_qwords >= PERF_X86_ZMM_QWORDS) + return true; + + return false; +} + +static inline bool event_needs_high16_zmm(struct perf_event *event) +{ + if (!(event->attr.sample_type & + (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER))) + return false; + + if (!event->attr.sample_simd_regs_enabled) + return false; + + if ((event->attr.sample_type & PERF_SAMPLE_REGS_INTR) && + (fls64(event->attr.sample_simd_vec_reg_intr) > PERF_X86_H16ZMM_BASE)) + return true; + + if ((event->attr.sample_type & PERF_SAMPLE_REGS_USER) && + (fls64(event->attr.sample_simd_vec_reg_user) > PERF_X86_H16ZMM_BASE)) + return true; + + return false; +} + struct amd_nb { int nb_id; /* NorthBridge id */ int refcnt; /* reference count */ diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index da77845e1f02..75394c4e8bc3 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -737,6 +737,14 @@ struct x86_perf_regs { u64 *ymmh_regs; struct ymmh_struct *ymmh; }; + union { + u64 *zmmh_regs; + struct avx_512_zmm_uppers_state *zmmh; + }; + union { + u64 *h16zmm_regs; + struct avx_512_hi16_state *h16zmm; + }; }; extern unsigned long perf_arch_instruction_pointer(struct pt_regs *regs); diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h index d544f6d79871..b88d0b6822fd 100644 --- a/arch/x86/include/uapi/asm/perf_regs.h +++ b/arch/x86/include/uapi/asm/perf_regs.h @@ -60,16 +60,20 @@ enum perf_event_x86_regs { enum { PERF_X86_SIMD_XMM_REGS = 16, PERF_X86_SIMD_YMM_REGS = 16, - PERF_X86_SIMD_VEC_REGS_MAX = PERF_X86_SIMD_YMM_REGS, + PERF_X86_SIMD_ZMM_REGS = 32, + PERF_X86_SIMD_VEC_REGS_MAX = PERF_X86_SIMD_ZMM_REGS, }; #define PERF_X86_SIMD_VEC_MASK __GENMASK_ULL(PERF_X86_SIMD_VEC_REGS_MAX - 1, 0) +#define PERF_X86_H16ZMM_BASE 16 + enum { /* 1 qword = 8 bytes */ PERF_X86_XMM_QWORDS = 2, PERF_X86_YMM_QWORDS = 4, - PERF_X86_SIMD_QWORDS_MAX = PERF_X86_YMM_QWORDS, + PERF_X86_ZMM_QWORDS = 8, + PERF_X86_SIMD_QWORDS_MAX = PERF_X86_ZMM_QWORDS, }; #endif /* _ASM_X86_PERF_REGS_H */ diff --git a/arch/x86/kernel/perf_regs.c b/arch/x86/kernel/perf_regs.c index 316d18c13c02..b4a584057fe4 100644 --- a/arch/x86/kernel/perf_regs.c +++ b/arch/x86/kernel/perf_regs.c @@ -78,6 +78,7 @@ u64 perf_reg_value(struct pt_regs *regs, int idx) } #define PERF_X86_YMMH_QWORDS (PERF_X86_YMM_QWORDS / 2) +#define PERF_X86_ZMMH_QWORDS (PERF_X86_ZMM_QWORDS / 2) u64 perf_simd_reg_value(struct pt_regs *regs, int idx, u16 qwords_idx, bool pred) @@ -95,6 +96,13 @@ u64 perf_simd_reg_value(struct pt_regs *regs, int idx, qwords_idx >= PERF_X86_SIMD_QWORDS_MAX)) return 0; + if (idx >= PERF_X86_H16ZMM_BASE) { + if (!perf_regs->h16zmm_regs) + return 0; + return perf_regs->h16zmm_regs[(idx - PERF_X86_H16ZMM_BASE) * + PERF_X86_ZMM_QWORDS + qwords_idx]; + } + if (qwords_idx < PERF_X86_XMM_QWORDS) { if (!perf_regs->xmm_regs) return 0; @@ -105,6 +113,11 @@ u64 perf_simd_reg_value(struct pt_regs *regs, int idx, return 0; return perf_regs->ymmh_regs[idx * PERF_X86_YMMH_QWORDS + qwords_idx - PERF_X86_XMM_QWORDS]; + } else if (qwords_idx < PERF_X86_ZMM_QWORDS) { + if (!perf_regs->zmmh_regs) + return 0; + return perf_regs->zmmh_regs[idx * PERF_X86_ZMMH_QWORDS + + qwords_idx - PERF_X86_YMM_QWORDS]; } return 0; @@ -126,7 +139,8 @@ int perf_simd_reg_validate(u64 sample_type, u16 simd_enabled, if (vec_qwords) { if (vec_qwords != PERF_X86_XMM_QWORDS && - vec_qwords != PERF_X86_YMM_QWORDS) + vec_qwords != PERF_X86_YMM_QWORDS && + vec_qwords != PERF_X86_ZMM_QWORDS) return -EINVAL; if (!vec_mask_intr && !vec_mask_user) return -EINVAL; -- 2.34.1