[RFC PATCH 04/22] dt-bindings: perf: ti,k3-ddr-pmu: Add K3 DDR PMU binding

[MANNURU VENKATESWARLU <v-mannuru@ti.com>]

From: Aarya Chaumal <a-chaumal@ti.com>

Add device tree binding for the DDR performance monitoring unit in TI K3
SoCs.

Signed-off-by: Aarya Chaumal <a-chaumal@ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
---
 .../bindings/perf/ti,k3-ddr-pmu.yaml          | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/perf/ti,k3-ddr-pmu.yaml

diff --git a/Documentation/devicetree/bindings/perf/ti,k3-ddr-pmu.yaml b/Documentation/devicetree/bindings/perf/ti,k3-ddr-pmu.yaml
new file mode 100644
index 0000000000000..575a51e406001
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/ti,k3-ddr-pmu.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/ti,k3-ddr-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 DDR performance monitor
+
+maintainers:
+  - Bryan Brattlof <bb@ti.com>
+
+description: |
+  TI K3 SoCs contain DDR performance counters inside the VBUSM to
+  Cadence AXI bridge within the DDR subsystem (SSCFG region). There
+  are four counters, each programmed independently via a 6-bit field
+  in a single control register. Each counter can track one of the
+  hardware events listed in the SoC Technical Reference Manual (e.g.
+  read commands, write commands, refresh cycles).
+
+properties:
+  compatible:
+    const: ti,k3-ddr-pmu
+
+  reg:
+    maxItems: 1
+    description: Counter select register and counter registers within
+      the DDR subsystem SSCFG address space.
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    ddr_pmu0: ddr-pmu@100 {
+        compatible = "ti,k3-ddr-pmu";
+        reg = <0x00 0x100 0x00 0x14>;
+    };
-- 
2.34.1