From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7FDA433E82; Mon, 3 Aug 2026 20:46:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785789970; cv=none; b=bVu/++qCG7Zaa5AkLDn2tzfKpvA4BDug1aF4kh0FORcVY1sDP+RQ2xNc7NrCCn9aSzrrWHSW9gvLAqP9SYuIHzHkF1rCR0vPM5Qyo6fy7pcBQX20+xPdWHBLoZX1WqahaU2tSfPoyl0OcYT2em03Kk+RBdnVgBX5Bpf85PLcm7E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785789970; c=relaxed/simple; bh=ALnTatgT1zqsGVlCcFSKQyK0Fj6JwajmVksosnr0ebQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Eeext++ocVONk+QQkblC+gYiHyilQsJvrQQGGSV6LwKdS1s2DZAmM3vsph3FGcMqsje78ODWsDCn5tIKkTKBhfcOXgWxsLgRV/9MCimjC4QImmtjcVe6qEw8EfYMyDqqHwmOr++2R147cADLfGFF7Dy1G8hMbH4b1qqq6UkaTAY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CMnFRJAw; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CMnFRJAw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785789969; x=1817325969; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ALnTatgT1zqsGVlCcFSKQyK0Fj6JwajmVksosnr0ebQ=; b=CMnFRJAwUAhCOCs84A1AZo8/EnOeAnAo6L1p04ELS9ri6UV/H0lC0Ohz c25cDC8nf87kA+C4RH08F2E+zeJtbB8wjzE2JdZzlFGTkChUPgD8OW1og vUjkWFsaT90TxTbAv6Dcuztf/VADtZCXcj48YMsXTSDJy+Yhd0elDcE9J 2mg95cbaCgyRJkhaGXQspgqIVhFgF02nhGhXtKGynLaQWEPG2t7MoCyFQ yru28IkFqYdkuBZ//ZNAtT+Ged8zL1rpC2UGQDD/OB16QWl7IUnDOlnaj dCUqm1EFb99XdHAgkzul2vJU+cs/2d0s+y5H5+lKjld4NQ1xLACxR/VWs A==; X-CSE-ConnectionGUID: TT4up+NgRFuA+AgwJHLZaA== X-CSE-MsgGUID: uw2OeUIPQCmSQLAk9pPX8g== X-IronPort-AV: E=McAfee;i="6800,10657,11864"; a="96927296" X-IronPort-AV: E=Sophos;i="6.25,203,1779174000"; d="scan'208";a="96927296" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2026 13:46:07 -0700 X-CSE-ConnectionGUID: stXH8QHeSlW7ALVcDgyFWA== X-CSE-MsgGUID: Kvfrwb4+SsmJKdnZsihL0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,203,1779174000"; d="scan'208";a="284702396" Received: from rosenzwe-mobl1.amr.corp.intel.com (HELO tfalcon-desk.attlocal.net) ([10.124.221.5]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2026 13:46:04 -0700 From: Thomas Falcon To: Namhyung Kim Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Dapeng Mi Subject: [PATCH v3 5/6] perf tools: Show memory region in perf-script subcommand Date: Mon, 3 Aug 2026 15:45:39 -0500 Message-ID: <20260803204540.100348-6-thomas.falcon@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803204540.100348-1-thomas.falcon@intel.com> References: <20260803204540.100348-1-thomas.falcon@intel.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Dapeng Mi Show the memory region in perf-script subcommand. Memory region is found in the mem_region field of the memory information data source. This field was included with the introduction of support for the Off-module Response facility (OMR) [1] in Intel's Diamond Rapids and Nova Lake Architectures. An example of perf-script output with the new memory region field is shown below: random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Yes|BLK N/A|Region N/A 7f32ae64a2ec random 2411a68201042 |OP LOAD|LVL RAM hit|SNP Hit|TLB L1 or L2 hit|LCK No|BLK N/A|Region Mem-1 561de7f8910a random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Yes|BLK N/A|Region N/A 7f32ae64a2d0 random 20e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Yes|BLK Data|Region N/A 7f32ae64a2d0 random 20e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Yes|BLK Data|Region N/A 7f32ae64a2d0 random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Yes|BLK N/A|Region N/A 7f32ae64a2ec random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Yes|BLK N/A|Region N/A 7f32ae64a2d0 random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Yes|BLK N/A|Region N/A 7f32ae64a2d0 random 2411a68201042 |OP LOAD|LVL RAM hit|SNP Hit|TLB L1 or L2 hit|LCK No|BLK N/A|Region Mem-1 561de7f8910a random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Yes|BLK N/A|Region N/A 7f32ae64a2ec random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Yes|BLK N/A|Region N/A 7f32ae64a2d0 [1]: https://lore.kernel.org/all/20260114011750.350569-1-dapeng1.mi@linux.intel.com/ Assisted-by: Sashiko:gemini-3.1-pro-preview Assisted-by: GitHub-Copilot:claude-opus-4-8 Signed-off-by: Dapeng Mi Signed-off-by: Thomas Falcon Link: https://lore.kernel.org/all/20260114011750.350569-1-dapeng1.mi@linux.intel.com/ --- v3: make memory region reporting conditional on feature bit --- tools/perf/builtin-script.c | 11 ++- tools/perf/util/mem-events.c | 77 +++++++++++++++++++ tools/perf/util/mem-events.h | 1 + .../scripting-engines/trace-event-python.c | 4 +- 4 files changed, 87 insertions(+), 6 deletions(-) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index f91d8b1fbd01..9ebf8dfe01c9 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -2081,8 +2081,8 @@ static int evlist__max_name_len(struct evlist *evlist) static int data_src__fprintf(u64 data_src, FILE *fp) { struct mem_info *mi = mem_info__new(); - char decode[100]; - char out[100]; + char decode[200]; + char out[200]; static int maxlen; int len; @@ -2090,10 +2090,10 @@ static int data_src__fprintf(u64 data_src, FILE *fp) return -ENOMEM; mem_info__data_src(mi)->val = data_src; - perf_script__meminfo_scnprintf(decode, 100, mi); + perf_script__meminfo_scnprintf(decode, 200, mi); mem_info__put(mi); - len = scnprintf(out, 100, "%16" PRIx64 " %s", data_src, decode); + len = scnprintf(out, 200, "%16" PRIx64 " %s", data_src, decode); if (maxlen < len) maxlen = len; @@ -4470,6 +4470,9 @@ int cmd_script(int argc, const char **argv) if (show_full_info) script.tool.show_feat_hdr = SHOW_FEAT_HEADER_FULL_INFO; + perf_mem__set_show_region(perf_header__has_feat(&session->header, + HEADER_MEMORY_RANGES)); + if (symbol__init(env) < 0) goto out_delete; diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 4fd48fd20055..61f203508916 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -31,6 +31,13 @@ struct perf_mem_event perf_mem_events[PERF_MEM_EVENTS__MAX] = { bool perf_mem_record[PERF_MEM_EVENTS__MAX] = { 0 }; +static bool perf_mem__show_region = false; + +void perf_mem__set_show_region(bool val) +{ + perf_mem__show_region = val; +} + struct perf_mem_event *perf_pmu__mem_events_ptr(struct perf_pmu *pmu, int i) { if (i >= PERF_MEM_EVENTS__MAX || !pmu) @@ -604,6 +611,72 @@ int perf_mem__blk_scnprintf(char *out, size_t sz, const struct mem_info *mem_inf return l; } +static int perf_mem__region_scnprintf(char *out, size_t sz, const struct mem_info *mem_info) +{ + size_t l = 0; + u64 mem = PERF_MEM_REGION_NA; + + sz -= 1; /* -1 for null termination */ + out[0] = '\0'; + + if (mem_info) + mem = mem_info__const_data_src(mem_info)->mem_region; + + switch (mem) { + case PERF_MEM_REGION_NA: + case PERF_MEM_REGION_RSVD: + l += scnprintf(out + l, sz - l, "N/A"); + break; + case PERF_MEM_REGION_L_SHARE: + l += scnprintf(out + l, sz - l, "Local-shared-cache"); + break; + case PERF_MEM_REGION_L_NON_SHARE: + l += scnprintf(out + l, sz - l, "Local-non-shared-cache"); + break; + case PERF_MEM_REGION_O_IO: + l += scnprintf(out + l, sz - l, "Other-IO"); + break; + case PERF_MEM_REGION_O_SHARE: + l += scnprintf(out + l, sz - l, "Other-shared-cache"); + break; + case PERF_MEM_REGION_O_NON_SHARE: + l += scnprintf(out + l, sz - l, "Other-non-shared-cache"); + break; + case PERF_MEM_REGION_MMIO: + l += scnprintf(out + l, sz - l, "MMIO"); + break; + case PERF_MEM_REGION_MEM0: + l += scnprintf(out + l, sz - l, "Mem-0"); + break; + case PERF_MEM_REGION_MEM1: + l += scnprintf(out + l, sz - l, "Mem-1"); + break; + case PERF_MEM_REGION_MEM2: + l += scnprintf(out + l, sz - l, "Mem-2"); + break; + case PERF_MEM_REGION_MEM3: + l += scnprintf(out + l, sz - l, "Mem-3"); + break; + case PERF_MEM_REGION_MEM4: + l += scnprintf(out + l, sz - l, "Mem-4"); + break; + case PERF_MEM_REGION_MEM5: + l += scnprintf(out + l, sz - l, "Mem-5"); + break; + case PERF_MEM_REGION_MEM6: + l += scnprintf(out + l, sz - l, "Mem-6"); + break; + case PERF_MEM_REGION_MEM7: + l += scnprintf(out + l, sz - l, "Mem-7"); + break; + default: + l += scnprintf(out + l, sz - l, "N/A"); + break; + } + + return l; +} + int perf_script__meminfo_scnprintf(char *out, size_t sz, const struct mem_info *mem_info) { int i = 0; @@ -620,6 +693,10 @@ int perf_script__meminfo_scnprintf(char *out, size_t sz, const struct mem_info * i += perf_mem__lck_scnprintf(out + i, sz - i, mem_info); i += scnprintf(out + i, sz - i, "|BLK "); i += perf_mem__blk_scnprintf(out + i, sz - i, mem_info); + if (perf_mem__show_region) { + i += scnprintf(out + i, sz - i, "|Region "); + i += perf_mem__region_scnprintf(out + i, sz - i, mem_info); + } return i; } diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h index daa22748f9fe..91fe57ce1859 100644 --- a/tools/perf/util/mem-events.h +++ b/tools/perf/util/mem-events.h @@ -146,5 +146,6 @@ enum mem_stat_dtlb { int mem_stat_index(const enum mem_stat_type mst, const u64 data_src); const char *mem_stat_name(const enum mem_stat_type mst, const int idx); +void perf_mem__set_show_region(bool val); #endif /* __PERF_MEM_EVENTS_H */ diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools/perf/util/scripting-engines/trace-event-python.c index 8f832ae316ca..57ec259897e4 100644 --- a/tools/perf/util/scripting-engines/trace-event-python.c +++ b/tools/perf/util/scripting-engines/trace-event-python.c @@ -695,7 +695,7 @@ static void set_sample_datasrc_in_dict(PyObject *dict, struct perf_sample *sample) { struct mem_info *mi = mem_info__new(); - char decode[100]; + char decode[200]; if (!mi) Py_FatalError("couldn't create mem-info"); @@ -704,7 +704,7 @@ static void set_sample_datasrc_in_dict(PyObject *dict, PyLong_FromUnsignedLongLong(sample->data_src)); mem_info__data_src(mi)->val = sample->data_src; - perf_script__meminfo_scnprintf(decode, 100, mi); + perf_script__meminfo_scnprintf(decode, 200, mi); mem_info__put(mi); pydict_set_item_string_decref(dict, "datasrc_decode", -- 2.55.0