From: Tengda Wu <wutengda@huaweicloud.com>
To: Namhyung Kim <namhyung@kernel.org>,
james.clark@linaro.org, xueshuai@linux.alibaba.com,
Adrian Hunter <adrian.hunter@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
leo.yan@linux.dev, Li Huafei <lihuafei1@huawei.com>,
Ian Rogers <irogers@google.com>,
Kim Phillips <kim.phillips@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Ingo Molnar <mingo@redhat.com>, Bill Wendling <morbo@google.com>,
Nick Desaulniers <nick.desaulniers+lkml@gmail.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Zecheng Li <zli94@ncsu.edu>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
llvm@lists.linux.dev, Tengda Wu <wutengda@huaweicloud.com>
Subject: [PATCH v5 14/26] perf annotate-data: Add arch_get_reg_offset helper
Date: Tue, 8 Sep 2026 13:01:10 +0000 [thread overview]
Message-ID: <20260908130122.633500-15-wutengda@huaweicloud.com> (raw)
In-Reply-To: <20260908130122.633500-1-wutengda@huaweicloud.com>
Add a helper to compute the effective offset from a base register
for instruction operands. Currently handles arm64 addressing modes
including post-indexed, single-register, SIB-style indexed with
shift/extension, and constant-offset register pairs.
Fallback to instruction's raw offset for other architectures.
Signed-off-by: Tengda Wu <wutengda@huaweicloud.com>
---
tools/perf/util/annotate-data.c | 106 +++++++++++++++++++++++++++-----
tools/perf/util/annotate-data.h | 4 +-
2 files changed, 94 insertions(+), 16 deletions(-)
diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-data.c
index c51b20a7af9b..754c0efe2077 100644
--- a/tools/perf/util/annotate-data.c
+++ b/tools/perf/util/annotate-data.c
@@ -1118,6 +1118,74 @@ static void setup_stack_canary(struct data_loc_info *dloc)
}
}
+int arch_get_reg_offset(const struct arch *arch, struct annotated_op_loc *op_loc,
+ int breg, struct type_state *state, bool apply_index,
+ int *offset)
+{
+ if (arch__is_arm64(arch)) {
+ int reg2;
+
+ /* Post-indexed addressing: offset is 0 when not applying index */
+ if (op_loc->addr_mode == PERF_AAM_POST_INDEX && !apply_index) {
+ *offset = 0;
+ return 0;
+ }
+
+ /* Single-register addressing: return the stored offset directly */
+ if (!op_loc->multi_regs) {
+ *offset = op_loc->offset;
+ return 0;
+ }
+
+ /*
+ * SIB (Scale-Index-Base) style indexed addressing, e.g.:
+ * Array element load: ldr dst, [base, index, lsl #3]
+ * Array element load: ldr dst, [base, index, uxtw #3]
+ * Array address calc: add dst, base, index lsl #3
+ *
+ * The index reg only computes element offset without modifying
+ * the underlying data type; the dst type is inherited from base.
+ * Therefore, the base reg offset can be treated as 0.
+ */
+ if (op_loc->extend_type || op_loc->shift_type) {
+ /* Memory references use the breg as the address base. */
+ if (op_loc->mem_ref) {
+ *offset = 0;
+ return 0;
+ }
+ /*
+ * Otherwise, require breg to be a known pointer type to
+ * avoid treating integer operations as address calculations.
+ */
+ if (has_reg_type(state, breg) && state->regs[breg].ok &&
+ (state->regs[breg].kind == TSR_KIND_POINTER ||
+ (state->regs[breg].kind == TSR_KIND_TYPE &&
+ dwarf_tag(&state->regs[breg].type) == DW_TAG_pointer_type))) {
+ *offset = 0;
+ return 0;
+ }
+ return -1;
+ }
+
+ /*
+ * For register-based addressing without shift/extension,
+ * reg2 may be a constant offset. Use its value as the offset
+ * from the base register.
+ */
+ reg2 = op_loc->reg1 == breg ? op_loc->reg2 : op_loc->reg1;
+ if (has_reg_type(state, reg2) && state->regs[reg2].ok &&
+ state->regs[reg2].kind == TSR_KIND_CONST) {
+ *offset = (s64)state->regs[reg2].imm_value;
+ return 0;
+ }
+
+ return -1;
+ }
+
+ *offset = op_loc->offset;
+ return 0;
+}
+
/*
* It's at the target address, check if it has a matching type.
* It returns PERF_TMR_BAIL_OUT when it looks up per-cpu variables which
@@ -1132,18 +1200,26 @@ static enum type_match_result check_matching_type(struct type_state *state,
Dwarf_Word size;
u32 insn_offset = dl->al.offset;
int reg = dloc->op->reg1;
- int offset = dloc->op->offset;
+ int offset;
const char *offset_sign = "";
bool retry = true;
- if (offset < 0) {
- offset = -offset;
- offset_sign = "-";
+again:
+ if (arch_get_reg_offset(dloc->arch, dloc->op, reg, state, false, &offset)) {
+ /*
+ * Fall back to the instruction's offset. This prevents the
+ * register type of the instruction from being completely lost.
+ * Compared to dropping this type inference entirely, providing
+ * a rough type hint is likely more useful.
+ */
+ offset = dloc->op->offset;
}
-again:
+ if (offset < 0)
+ offset_sign = "-";
+
pr_debug_dtp("chk [%x] reg%d offset=%s%#x ok=%d kind=%d ",
- insn_offset, reg, offset_sign, offset,
+ insn_offset, reg, offset_sign, abs(offset),
state->regs[reg].ok, state->regs[reg].kind);
if (!state->regs[reg].ok)
@@ -1166,7 +1242,7 @@ static enum type_match_result check_matching_type(struct type_state *state,
*/
ptr_type = die_get_pointer_type(&state->regs[reg].type, &ptr_die);
if (!ptr_type) {
- if (dloc->op->offset < 0 && reg != state->stack_reg)
+ if (offset < 0 && reg != state->stack_reg)
goto check_kernel;
return PERF_TMR_NO_POINTER;
@@ -1176,7 +1252,7 @@ static enum type_match_result check_matching_type(struct type_state *state,
if (__die_get_real_type(ptr_type, type_die) == NULL)
return PERF_TMR_NO_POINTER;
- dloc->type_offset = dloc->op->offset + state->regs[reg].offset;
+ dloc->type_offset = offset + state->regs[reg].offset;
if (dwarf_tag(type_die) == DW_TAG_typedef)
die_get_real_type(type_die, &sized_type);
@@ -1205,7 +1281,7 @@ static enum type_match_result check_matching_type(struct type_state *state,
*/
*type_die = state->regs[reg].type;
- dloc->type_offset = dloc->op->offset + state->regs[reg].offset;
+ dloc->type_offset = offset + state->regs[reg].offset;
/* Get the size of the actual type */
if (dwarf_aggregate_size(type_die, &size) < 0 ||
@@ -1224,7 +1300,7 @@ static enum type_match_result check_matching_type(struct type_state *state,
*/
*type_die = state->regs[reg].type;
- dloc->type_offset = dloc->op->offset;
+ dloc->type_offset = offset;
/* Get the size of the actual type */
if (dwarf_aggregate_size(type_die, &size) < 0 ||
@@ -1248,7 +1324,7 @@ static enum type_match_result check_matching_type(struct type_state *state,
}
if (state->regs[reg].kind == TSR_KIND_PERCPU_BASE) {
- u64 var_addr = dloc->op->offset;
+ u64 var_addr = (s64) offset;
int var_offset;
pr_debug_dtp("percpu var");
@@ -1275,7 +1351,7 @@ static enum type_match_result check_matching_type(struct type_state *state,
if (state->regs[reg].kind == TSR_KIND_CONST &&
dso__kernel(map__dso(dloc->ms->map))) {
- if (dloc->op->offset < 0 && reg != state->stack_reg && reg != dloc->fbreg)
+ if (offset < 0 && reg != state->stack_reg && reg != dloc->fbreg)
goto check_kernel;
}
check_non_register:
@@ -1362,7 +1438,7 @@ static enum type_match_result check_matching_type(struct type_state *state,
arch__is_x86(dloc->arch)) {
pr_debug_dtp("this-cpu var");
- addr = dloc->op->offset;
+ addr = (s64) offset;
if (get_global_var_type(cu_die, dloc, dloc->ip, addr,
&offset, type_die)) {
@@ -1373,8 +1449,8 @@ static enum type_match_result check_matching_type(struct type_state *state,
}
/* Access to global variable like "-0x7dcf0500(,%rdx,8)" */
- if (dloc->op->offset < 0 && reg != state->stack_reg) {
- addr = (s64) dloc->op->offset;
+ if (offset < 0 && reg != state->stack_reg) {
+ addr = (s64) offset;
if (get_global_var_type(cu_die, dloc, dloc->ip, addr,
&offset, type_die)) {
diff --git a/tools/perf/util/annotate-data.h b/tools/perf/util/annotate-data.h
index 453e13bbe3e2..e6ca47e25e04 100644
--- a/tools/perf/util/annotate-data.h
+++ b/tools/perf/util/annotate-data.h
@@ -265,7 +265,9 @@ bool get_global_var_type(Dwarf_Die *cu_die, struct data_loc_info *dloc,
bool get_global_var_info(struct data_loc_info *dloc, u64 addr,
const char **var_name, int *var_offset);
void pr_debug_type_name(Dwarf_Die *die, enum type_state_kind kind);
-
+int arch_get_reg_offset(const struct arch *arch, struct annotated_op_loc *op_loc,
+ int breg, struct type_state *state, bool apply_index,
+ int *offset);
#else /* HAVE_LIBDW_SUPPORT */
static inline struct annotated_data_type *
--
2.34.1
next prev parent reply other threads:[~2026-09-08 13:02 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-08 13:00 [PATCH v5 00/26] perf arm64: Support data type profiling Tengda Wu
2026-09-08 13:00 ` [PATCH v5 01/26] perf capstone: Symbolize address operands to match objdump on arm64 Tengda Wu
2026-09-08 13:00 ` [PATCH v5 02/26] perf llvm: Fix arm64 adrp instruction disassembly mismatch with objdump Tengda Wu
2026-09-08 13:00 ` [PATCH v5 03/26] perf annotate-arm64: Generalize arm64_mov__parse to support more instructions Tengda Wu
2026-09-08 13:01 ` [PATCH v5 04/26] perf annotate-arm64: Handle load and store instructions Tengda Wu
2026-09-08 13:01 ` [PATCH v5 05/26] perf annotate: Normalize arch__dwarf_regnum() error return values Tengda Wu
2026-09-08 13:01 ` [PATCH v5 06/26] perf annotate: Introduce extract_op_location callback for arch-specific parsing Tengda Wu
2026-09-08 13:01 ` [PATCH v5 07/26] perf dwarf-regs: Adapt get_dwarf_regnum() for arm64 Tengda Wu
2026-09-08 18:08 ` Ian Rogers
2026-09-11 1:47 ` Tengda Wu
2026-09-08 13:01 ` [PATCH v5 08/26] perf annotate: Adapt arch__dwarf_regnum() " Tengda Wu
2026-09-08 13:01 ` [PATCH v5 09/26] perf annotate-arm64: Implement extract_op_location() callback Tengda Wu
2026-09-08 13:01 ` [PATCH v5 10/26] perf annotate: Default to --itrace=i1i for data type profiling Tengda Wu
2026-09-08 13:01 ` [PATCH v5 11/26] perf arm-spe: Set default synthesized event period to 1 Tengda Wu
2026-09-08 13:01 ` [PATCH v5 12/26] perf annotate-data: Extract invalidate_reg_state() as a common helper Tengda Wu
2026-09-08 13:01 ` [PATCH v5 13/26] perf annotate-arm64: Enable instruction tracking support Tengda Wu
2026-09-08 13:01 ` Tengda Wu [this message]
2026-09-08 13:01 ` [PATCH v5 15/26] perf annotate-arm64: Track return type after call instructions Tengda Wu
2026-09-08 13:01 ` [PATCH v5 16/26] perf annotate-arm64: Support load instruction tracking Tengda Wu
2026-09-08 13:01 ` [PATCH v5 17/26] perf annotate-arm64: Support store " Tengda Wu
2026-09-08 13:01 ` [PATCH v5 18/26] perf annotate-data: Expand type_state_reg imm_value to u64 Tengda Wu
2026-09-08 13:01 ` [PATCH v5 19/26] perf annotate-data: Track imm_value for stack variables Tengda Wu
2026-09-08 13:01 ` [PATCH v5 20/26] perf annotate-x86: Delete stale stack state on store of untracked register Tengda Wu
2026-09-08 13:01 ` [PATCH v5 21/26] perf annotate-arm64: Support stack variable tracking Tengda Wu
2026-09-08 13:01 ` [PATCH v5 22/26] perf annotate-arm64: Support 'mov' instruction tracking Tengda Wu
2026-09-08 13:01 ` [PATCH v5 23/26] perf annotate-arm64: Support 'add' " Tengda Wu
2026-09-08 13:18 ` [PATCH v5 00/26] perf arm64: Support data type profiling Tengda Wu
-- strict thread matches above, loose matches on Subject: below --
2026-09-08 13:05 Tengda Wu
2026-09-08 13:05 ` [PATCH v5 14/26] perf annotate-data: Add arch_get_reg_offset helper Tengda Wu
2026-09-08 13:22 ` sashiko-bot
2026-09-10 12:13 ` Tengda Wu
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