From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dggsgout11.his.huawei.com (dggsgout11.his.huawei.com [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65CB254A7FF; Tue, 8 Sep 2026 13:02:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872551; cv=none; b=h0XaxfTkpzZOntZuBxzQ3HYvmsbnCvklFKsMTbCA+TBhV/PhJj820+b7HyjsFYKuTi4oEHDb9KR+QI/wvAtwEgZwu3+MZYBj88NazUUmnheVpg5eHnsJLUUUPF5++m/iz4Ms2QiSiVQOx57L+NbZuir0xmiErWB6GTFSO6X4UQs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788872551; c=relaxed/simple; bh=WkLaZun02m9M3g8IXoovbpbpJ5MgOqi819t+HLC/GRc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=vFz7xvjGC7ygW9elHJBvyEIFP8AvfWevOLS9fyAJQi5qq2qmXPDb7nKH9EHvJ1Mq8+CnzJEh+oRnFbrrizCay+yTCChF8I+iaBjHWCQmv33yzkQSecmRMCmZ4oE8LvF1UJSsTZAg+8mJpDMMiOh1V6o0wJF69i6XMJ5bQp9ZLpk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.198]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4hfPFX1FylzYQvVm; Tue, 8 Sep 2026 21:01:04 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.128]) by mail.maildlp.com (Postfix) with ESMTP id AB41540577; Tue, 8 Sep 2026 21:01:55 +0800 (CST) Received: from huawei.com (unknown [10.67.174.45]) by APP4 (Coremail) with UTF8SMTPA id gCh0CgAni5gpB6BqC9rlBA--.34632S24; Tue, 08 Sep 2026 21:01:54 +0800 (CST) From: Tengda Wu To: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Adrian Hunter Cc: Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Tengda Wu Subject: [PATCH v5 22/26] perf annotate-arm64: Support 'mov' instruction tracking Date: Tue, 8 Sep 2026 13:01:18 +0000 Message-Id: <20260908130122.633500-23-wutengda@huaweicloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260908130122.633500-1-wutengda@huaweicloud.com> References: <20260908130122.633500-1-wutengda@huaweicloud.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:gCh0CgAni5gpB6BqC9rlBA--.34632S24 X-Coremail-Antispam: 1UD129KBjvJXoWxKw15JF18trWxGr4fGw47XFb_yoW7GFWrpa 1DCw15G39Fqr42grsIqF47Xr9a9w4Igr12kryqq39IyFW3tr1rKa97tFWavF45JrykCw17 Ja1DKFW5Xw42kaUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQq14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr1j6r xdM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkF7I0En4kS14v26r4a6rW5MxkF7I0Ew4C26cxK6c8Ij28IcwCF04k20xvY0x0E wIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E74 80Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0 I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr1j6rxdMIIF0xvE42 xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWxJVW8Jr1lIxAIcVC2z280aVCY 1x0267AKxVWxJr0_GcJvcSsGvfC2KfnxnUUI43ZEXa7sR_hiSJUUUUU== X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ Extend update_insn_state_arm64() to support register-to-register and immediate-to-register 'mov' instructions. For register-to-register 'mov' (e.g., mov dreg, sreg), propagate data type information from the source register to the destination register. For immediate-to-register 'mov' (e.g., mov dreg, #imm), store the immediate value in the destination register's imm_value field and set its kind to TSR_KIND_CONST, allowing subsequent instructions to resolve it as a constant. A real-world example is shown below: ffff8000803eebf8 : ffff8000803eec20: mov x21, x0 // x0 (struct vm_area_struct*) -> x21 ffff8000803eec28: ldr x2, [x0, #112] ffff8000803eec2c: cbz x2, ffff8000803eec94 * ffff8000803eec94: ldr x0, [x21, #152] Before this commit, the type of x21 was unknown, causing the subsequent inference to fail: var [0] reg0 offset 0 type='struct vm_area_struct*' size=0x8 chk [9c] reg21 offset=0x98 ok=0 kind=0 cfa : no type information final result: no type information After this commit, the type of x21 is correctly inferred as 'vm_area_struct': var [0] reg0 offset 0 type='struct vm_area_struct*' size=0x8 mov [28] reg0 -> reg21 type='struct vm_area_struct*' size=0x8 chk [9c] reg21 offset=0x98 ok=1 kind=1 (struct vm_area_struct*) : Good! found by insn track: 0x98(reg21) type-offset=0x98 final result: type='struct vm_area_struct' size=0xb0 Signed-off-by: Tengda Wu --- .../perf/util/annotate-arch/annotate-arm64.c | 60 ++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/util/annotate-arch/annotate-arm64.c index d520975c5936..2f8bedf583c1 100644 --- a/tools/perf/util/annotate-arch/annotate-arm64.c +++ b/tools/perf/util/annotate-arch/annotate-arm64.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include #include +#include #include #include #include @@ -605,6 +606,7 @@ static int propagate_load_reg_state(struct type_state *state, tsr->type = type_die; tsr->kind = TSR_KIND_TYPE; tsr->offset = 0; + tsr->imm_value = 0; tsr->ok = true; if (src->multi_regs) { @@ -810,6 +812,58 @@ static void update_store_insn_state(struct type_state *state, adjust_reg_index_state(state, dloc, dl, dst); } +static void update_mov_insn_state(struct type_state *state, + struct disasm_line *dl, + struct annotated_op_loc *src, + struct annotated_op_loc *dst) +{ + struct type_state_reg *tsr; + u32 insn_offset = dl->al.offset; + int sreg = src->reg1; + int dreg = dst->reg1; + + if (!has_reg_type(state, dreg)) + return; + + tsr = &state->regs[dreg]; + tsr->copied_from = -1; + + if (src->imm) { + invalidate_reg_state(tsr); + tsr->kind = TSR_KIND_CONST; + tsr->imm_value = (s64)src->offset; + tsr->offset = 0; + tsr->ok = true; + + pr_debug_dtp("mov [%x] imm=%#"PRIx64" -> reg%d\n", + insn_offset, tsr->imm_value, dreg); + return; + } + + if (!has_reg_type(state, sreg) || !state->regs[sreg].ok) { + invalidate_reg_state(tsr); + return; + } + + tsr->type = state->regs[sreg].type; + tsr->kind = state->regs[sreg].kind; + tsr->imm_value = state->regs[sreg].imm_value; + tsr->offset = state->regs[sreg].offset; + tsr->ok = state->regs[sreg].ok; + /* + * lifetime_active and lifetime_end represent DWARF variable lifetime + * ranges tied to the source register. Copying them risks incorrectly + * invalidating the destination register after a call instruction, + * so intentionally omit them. + */ + + if (tsr->kind == TSR_KIND_TYPE || tsr->kind == TSR_KIND_POINTER) + tsr->copied_from = sreg; + + pr_debug_dtp("mov [%x] reg%d -> reg%d", insn_offset, sreg, dreg); + pr_debug_type_name(&tsr->type, tsr->kind); +} + static void update_insn_state_arm64(struct type_state *state, struct data_loc_info *dloc, Dwarf_Die *cu_die, struct disasm_line *dl) @@ -876,6 +930,7 @@ static void update_insn_state_arm64(struct type_state *state, * prevent stale type info from propagating to subsequent instructions. */ if (has_reg_type(state, dst->reg1) && !dst->mem_ref && + strcmp(dl->ins.name, "mov") && !is_standard_load_insn(dl->ins.name)) { pr_debug_dtp("%s [%x] invalidate reg%d", dl->ins.name, insn_offset, dst->reg1); @@ -888,8 +943,11 @@ static void update_insn_state_arm64(struct type_state *state, return; } + /* Register to register or imm value to register transfers */ + if (!strcmp(dl->ins.name, "mov")) + update_mov_insn_state(state, dl, src, dst); /* Memory to register transfers */ - if (is_standard_load_insn(dl->ins.name)) + else if (is_standard_load_insn(dl->ins.name)) update_load_insn_state(state, dloc, dl, src, dst); /* Register to memory transfers */ else if (is_standard_store_insn(dl->ins.name)) -- 2.34.1