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AKwUvBxG3o34qD+BbBimVehr6cfsJ6mSEK3EoVKZSC2THOfbb2izzsNA8J3OHx90yibPx2cB5CY++8XyC+td+OnuwOGO@vger.kernel.org X-Gm-Message-State: AFuF++kGzJbrOPPS11NgBY3bo1zx/2d4hc37zDZeitF2JO16I9n1mXQA DuQp2Yy4SdigV+VMqX6KTon6b/IECsBWOuBwF7PFhZPzBDwbPobfr2YC9YZGixlEvmqm2J4T6UJ KOV718Q== X-Received: from pjbml8.prod.google.com ([2002:a17:90b:3608:b0:3a0:40b2:70ad]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90a:d648:b0:39e:6c6a:4b6e with SMTP id 98e67ed59e1d1-39e6c6a549dmr10605450a91.56.1790018071987; Mon, 21 Sep 2026 12:14:31 -0700 (PDT) Reply-To: Sean Christopherson Date: Mon, 21 Sep 2026 12:14:18 -0700 In-Reply-To: <20260921191418.950933-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260921191418.950933-1-seanjc@google.com> X-Mailer: git-send-email 2.55.0.1082.g2b9226bbc0-goog Message-ID: <20260921191418.950933-11-seanjc@google.com> Subject: [PATCH v4 10/10] perf/x86/intel: Check only PMC bits in PEBS_ENABLED when detecting host PEBS usage From: Sean Christopherson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Dapeng Mi , Jim Mattson , Mingwei Zhang , Stephane Eranian , Sashiko Bot Content-Type: text/plain; charset="UTF-8" When checking to see if guest PEBS usage should be disabled due to host PEBS usage, filter out non-counter bits in PEBS_ENABLE to avoid getting false positives in the unlikely scenario that "Enable Precise Store" is enabled without PEBS actually being active for any PMCs. Note, the other "hidden" usage of pebs_mask is already explicitly masked with intel_ctrl: .guest = intel_ctrl & ~cpuc->intel_ctrl_exclude_guest_mask & ~pebs_mask, I.e. removing the non-counter bits from pebs_mask doesn't change the value that is loaded into arr[global_ctrl].guest. Fixes: 854250329c02 ("KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations") Suggested-by: Dapeng Mi Reported-by: Sashiko Bot Closes: https://lore.kernel.org/all/20260508234018.F06AEC2BCB0@smtp.kernel.org Signed-off-by: Sean Christopherson --- arch/x86/events/intel/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index d9315bb2f221..1ff0586c7b71 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5323,7 +5323,7 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); - u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; + u64 pebs_mask = intel_ctrl & cpuc->pebs_enabled & x86_pmu.pebs_capable; u64 guest_pebs_mask; int global_ctrl; @@ -5375,7 +5375,7 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, * the guest wants to use for PEBS, (c) are not excluded from counting * in the guest, and (d) _are_ excluded from counting in the host. */ - guest_pebs_mask = pebs_mask & intel_ctrl & guest_pebs->enable & + guest_pebs_mask = pebs_mask & guest_pebs->enable & ~cpuc->intel_ctrl_exclude_guest_mask & cpuc->intel_ctrl_exclude_host_mask; -- 2.55.0.1082.g2b9226bbc0-goog