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AKwUvByyjnKN1prWq0tqPMYIKJG9xfUCM70w+hDtg7JHTTSwEDMelwuGrdn9NPX0wz0er6p7RCJLbzV5L0Df63wjY9Ik@vger.kernel.org X-Gm-Message-State: AFuF++nThg8ZrtsL7QDbjs/HHaydWR7hphgA6kgnt1sUh/j0oP0ad+qQ buzD68rCRx3irKz4uORmnpe4//s/gSyphQ5oMxrE7uWOp3FArh34LV9KfRGFRr3X/nNHcEF5YjE 3p2b/aQ== X-Received: from pgdj21.prod.google.com ([2002:a05:6a02:5215:b0:cc7:4a9d:af5f]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:140a:b0:3dd:a196:69ec with SMTP id adf61e73a8af0-3dda1967806mr11525924637.71.1790018061422; Mon, 21 Sep 2026 12:14:21 -0700 (PDT) Reply-To: Sean Christopherson Date: Mon, 21 Sep 2026 12:14:09 -0700 In-Reply-To: <20260921191418.950933-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260921191418.950933-1-seanjc@google.com> X-Mailer: git-send-email 2.55.0.1082.g2b9226bbc0-goog Message-ID: <20260921191418.950933-2-seanjc@google.com> Subject: [PATCH v4 01/10] perf/x86/intel: Ensure guest PEBS path doesn't set unwanted PERF_GLOBAL_CTRL bits From: Sean Christopherson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Dapeng Mi , Jim Mattson , Mingwei Zhang , Stephane Eranian , Sashiko Bot Content-Type: text/plain; charset="UTF-8" When reinstating PEBS counters into PERF_GLOBAL_CTRL for a KVM guest, mask the value with perf's desired/original PERF_GLOBAL_CTRL value to ensure KVM doesn't unintentionally set reserved bits in PERF_GLOBAL_CTRL. E.g. if the guest's PEBS_ENABLE value had bit 63, "Enable Precise Store", set, then using the raw guest PEBS value would propagate bit 63 to the guest's PERF_GLOBAL_CTRL value (which thankfully would be a failed VM-Entry, not a VMX Abort). The only reason this bug isn't reachable is because KVM doesn't support "Enable Precise Store" (which is probably a KVM bug?), i.e. bit 63 can't be set in kvm_pmu->pebs_enable and thus not in arr[pebs_enable].guest. In other words, this _should_ be a glorified nop in the current code base. Fixes: c59a1f106f5c ("KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS") Reviewed-by: Dapeng Mi Signed-off-by: Sean Christopherson --- arch/x86/events/intel/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index e36f340e2dc2..f4674d93a5e2 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5392,7 +5392,7 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ - arr[global_ctrl].guest |= arr[pebs_enable].guest; + arr[global_ctrl].guest |= intel_ctrl & arr[pebs_enable].guest; } return arr; -- 2.55.0.1082.g2b9226bbc0-goog