From: sashiko-bot@kernel.org
To: "Leo Yan" <leo.yan@arm.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [PATCH v2 14/14] perf tests: Check CoreSight emulated instruction entry and exit
Date: Wed, 23 Sep 2026 16:56:50 +0000 [thread overview]
Message-ID: <20260923165650.C62F61F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260923-perf_cs_etm_fix_non_taken-v2-14-6ab8c07a5455@arm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] perf tests: test flakiness due to page faults on the emulated MRS instruction
--
commit 2d0bd9a9a4d9e3186e0f8fab3a726c18a86eb407
Author: Leo Yan <leo.yan@arm.com>
perf tests: Check CoreSight emulated instruction entry and exit
This commit adds a test to check CoreSight emulated instruction entry and
exit by recording traploop's EL0 read of ID_AA64ISAR0_EL1. It uses
instruction encoding to filter out irrelevant exceptions like page faults,
expecting a 4-byte PC advance for the emulated MRS instruction.
> diff --git a/tools/perf/tests/shell/coresight/trap_entry_exit.sh b/tools/perf/tests/shell/coresight/trap_entry_exit.sh
> new file mode 100755
> index 0000000000000..3ebd4033b247a
> --- /dev/null
> +++ b/tools/perf/tests/shell/coresight/trap_entry_exit.sh
> @@ -0,0 +1,24 @@
> +#!/bin/bash
> +# SPDX-License-Identifier: GPL-2.0
> +# CoreSight emulated instruction entry and exit (exclusive)
> +
> +# shellcheck source=../lib/coresight_exception.sh
> +. "$(dirname "$0")/../lib/coresight_exception.sh"
> +
> +test_trap_entry_exit()
> +{
[ ... ]
> + decode_trace || return 1
> + # Page faults also appear as "int", but retry the same PC. Select MRS
> + # Xt, ID_AA64ISAR0_EL1 by its encoding; the low five bits select Xt.
> + check_exception_pairs "int.*insn: [01][[:xdigit:]] 06 38 d5" "iret" 4 || return 1
[Severity: Medium]
Will this test become flaky if an instruction page fault occurs exactly on
the MRS instruction itself?
The test filters events using the MRS instruction encoding to skip
irrelevant page faults. However, if a page fault happens directly on the
MRS instruction, the exception type is still int and the fetched
instruction bytes will match the MRS encoding.
When the page fault is resolved, the kernel returns via iret to retry the
exact same PC, resulting in a PC difference of 0.
Since check_exception_pairs strictly enforces a PC difference of 4 for all
matched pairs, wouldn't this 0-byte advance cause the test to falsely
fail?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260923-perf_cs_etm_fix_non_taken-v2-0-6ab8c07a5455@arm.com?part=14
next prev parent reply other threads:[~2026-09-23 16:56 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 15:21 [PATCH v2 00/14] perf cs-etm: Fix bogus branch samples on exceptions Leo Yan
2026-09-23 15:21 ` [PATCH v2 01/14] perf sample: Allow decoders to supply branch return addresses Leo Yan
2026-09-23 15:29 ` sashiko-bot
2026-09-24 13:00 ` Adrian Hunter
2026-09-23 15:21 ` [PATCH v2 02/14] perf intel-pt: Preserve return addresses for asynchronous branches Leo Yan
2026-09-23 15:43 ` sashiko-bot
2026-09-24 13:00 ` Adrian Hunter
2026-09-23 15:21 ` [PATCH v2 03/14] perf cs-etm: Break branch history when instruction memory is unavailable Leo Yan
2026-09-23 15:46 ` sashiko-bot
2026-09-23 15:21 ` [PATCH v2 04/14] perf cs-etm: Centralize packet ISA initialization Leo Yan
2026-09-23 15:50 ` sashiko-bot
2026-09-23 15:21 ` [PATCH v2 05/14] perf cs-etm: Use the recorded instruction size for A32 and A64 Leo Yan
2026-09-23 16:01 ` sashiko-bot
2026-09-29 13:55 ` James Clark
2026-09-23 15:21 ` [PATCH v2 06/14] perf cs-etm: Mark branches that were not taken Leo Yan
2026-09-23 16:09 ` sashiko-bot
2026-09-23 15:21 ` [PATCH v2 07/14] perf cs-etm: Factor out final instruction sample synthesis Leo Yan
2026-09-23 16:13 ` sashiko-bot
2026-09-23 15:21 ` [PATCH v2 08/14] perf cs-etm: Centralize branch sample synthesis checks Leo Yan
2026-09-23 16:18 ` sashiko-bot
2026-09-23 15:21 ` [PATCH v2 09/14] perf cs-etm: Classify exception calls using the exception packet Leo Yan
2026-09-23 16:24 ` sashiko-bot
2026-09-29 14:08 ` James Clark
2026-09-23 15:21 ` [PATCH v2 10/14] perf cs-etm: Synthesize exception entries separately from branches Leo Yan
2026-09-23 16:36 ` sashiko-bot
2026-09-23 15:21 ` [PATCH v2 11/14] perf tests: Check CoreSight IRQ entry and exit Leo Yan
2026-09-23 16:40 ` sashiko-bot
2026-09-29 12:22 ` James Clark
2026-09-23 15:21 ` [PATCH v2 12/14] perf tests: Check CoreSight syscall " Leo Yan
2026-09-23 16:46 ` sashiko-bot
2026-09-23 15:21 ` [PATCH v2 13/14] perf tests: Check CoreSight abort " Leo Yan
2026-09-23 16:49 ` sashiko-bot
2026-09-23 15:21 ` [PATCH v2 14/14] perf tests: Check CoreSight emulated instruction " Leo Yan
2026-09-23 16:56 ` sashiko-bot [this message]
2026-09-29 14:41 ` [PATCH v2 00/14] perf cs-etm: Fix bogus branch samples on exceptions James Clark
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260923165650.C62F61F000FF@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=leo.yan@arm.com \
--cc=linux-perf-users@vger.kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox