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AKwUvBwEoD7pc4ZNCaqdLDJpHsbvwWJvHmnyKAoJCMlmQbXstO4XtmjKrVtlZ930CAcPHi+Sa+cJdE2e0Y1gIfkyfTuH@vger.kernel.org X-Gm-Message-State: AFuF++mAV4GEFlyysSIrbFgQs9AOLds9NNQX8+R6xXsF6R+xVdLX9vHo xQUphC28ZnaQB1FeCgXO3JbDScHtiF8Men9YkqBAjD/nJYf/BANBgOzSMiP8MjTy5X90ZVtRGox 0IdeU4loesg== X-Received: from dyaw3-n1.prod.google.com ([2002:a05:693c:4143:10b0:33e:643c:91ec]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a05:7300:561e:b0:333:b6d8:c2fe with SMTP id 5a478bee46e88-3400439cfbcmr994696eec.3.1790228310933; Wed, 23 Sep 2026 22:38:30 -0700 (PDT) Date: Wed, 23 Sep 2026 22:36:40 -0700 In-Reply-To: <20260924053645.3555041-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260924053645.3555041-1-irogers@google.com> X-Mailer: git-send-email 2.56.0.rc1.310.g51773c2048-goog Message-ID: <20260924053645.3555041-17-irogers@google.com> Subject: [PATCH v1 16/21] perf vendor events intel: Update pantherlake events from 1.07 to 1.08 From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , "=?UTF-8?q?Andreas=20F=C3=A4rber?=" , Manivannan Sadhasivam , Dapeng Mi , Chun-Tse Shao , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable The updated events were published in: https://github.com/intel/perfmon/commit/f3bbfcf86d67948fc330d4b2cddb29408= 7663da4 Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- tools/perf/pmu-events/arch/x86/pantherlake/other.json | 10 ++++++++++ .../perf/pmu-events/arch/x86/pantherlake/pipeline.json | 6 +++--- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index f7c8c2aa476a..b8730fb35c31 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -27,7 +27,7 @@ GenuineIntel-6-(AA|AC|B5),v1.23,meteorlake,core GenuineIntel-6-1[AEF],v4,nehalemep,core GenuineIntel-6-2E,v4,nehalemex,core GenuineIntel-18-[13],v1.04,novalake,core -GenuineIntel-6-(CC|D5|E5),v1.07,pantherlake,core +GenuineIntel-6-(CC|D5|E5),v1.08,pantherlake,core GenuineIntel-6-A7,v1.04,rocketlake,core GenuineIntel-6-2A,v19,sandybridge,core GenuineIntel-6-8F,v1.39,sapphirerapids,core diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/other.json b/tools/= perf/pmu-events/arch/x86/pantherlake/other.json index 91dd2d25ebaf..840486ef592e 100644 --- a/tools/perf/pmu-events/arch/x86/pantherlake/other.json +++ b/tools/perf/pmu-events/arch/x86/pantherlake/other.json @@ -28,6 +28,16 @@ "UMask": "0x1", "Unit": "cpu_atom" }, + { + "BriefDescription": "LBR record is inserted [This event is alias t= o MISC_RETIRED.LBR_INSERTS]", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "EventCode": "0xe4", + "EventName": "LBR_INSERTS.ANY", + "PublicDescription": "LBR record is inserted [This event is alias = to MISC_RETIRED.LBR_INSERTS] Available PDIST counters: 0,1", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts streaming stores that have any type of= response.", "Counter": "0,1,2,3,4,5,6,7,8,9", diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json b/too= ls/perf/pmu-events/arch/x86/pantherlake/pipeline.json index 74209da5bc27..79747c8807bd 100644 --- a/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json @@ -1334,7 +1334,7 @@ "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xc0", "EventName": "INST_RETIRED.REP_ITERATION", - "PublicDescription": "Number of iterations of Repeat (REP) string = retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, a= nd doubleword version and string instructions can be repeated using a repet= ition prefix, REP, that allows their architectural execution to be repeated= a number of times as specified by the RCX register. Note: Since the number= of iterations within a REP instruction can be significantly affected by fa= st strings, this event may vary run to run and not match the architectural = number of iterations (specified by RCX) Available PDIST counters: 0,1", + "PublicDescription": "Number of iterations of Repeat (REP) string = retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, a= nd doubleword version and string instructions can be repeated using a repet= ition prefix, REP, that allows their architectural execution to be repeated= a number of times as specified by the RCX register. Note: Since the number= of iterations within a REP instruction can be significantly affected by fa= st strings, this event may vary from run to run and not match the architect= ural number of iterations (specified by RCX). Available PDIST counters: 0,1= ", "SampleAfterValue": "2000003", "UMask": "0x8", "Unit": "cpu_core" @@ -1860,11 +1860,11 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "LBR record is inserted", + "BriefDescription": "LBR record is inserted [This event is alias t= o LBR_INSERTS.ANY]", "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xe4", "EventName": "MISC_RETIRED.LBR_INSERTS", - "PublicDescription": "LBR record is inserted Available PDIST count= ers: 0,1", + "PublicDescription": "LBR record is inserted [This event is alias = to LBR_INSERTS.ANY] Available PDIST counters: 0,1", "SampleAfterValue": "1000003", "UMask": "0x1", "Unit": "cpu_core" --=20 2.56.0.rc1.310.g51773c2048-goog