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AKwUvByn6JsXZU9ANBevhXryPisN+CRe3P7gtjxIn3T7opAZSOm/3OTZLQGaL4td+FjbVUqQ6tNUsUeYlolfHzpGuEn+@vger.kernel.org X-Gm-Message-State: AFuF++k/eEutBqQAdmADcG0l1BtJmv9Jcng+4DWb4MS5Wi9MyWDC9thd LgwDUc0L4QW6+9O4YOfOsk5XqqwLH0908FvxfNV8bNV3cnuQzZLi7LjbKGsyD+kVMkjqW5I4wQd q+Kt7xaM9b27j1EUSpFYYM1T+0Q== X-Received: from jalg14.prod.google.com ([2002:a05:6638:c4e:b0:5f0:cbe4:72e7]) (user=coltonlewis job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6808:1394:b0:4b5:5bfb:f25e with SMTP id 5614622812f47-4d72c637812mr3680802b6e.21.1790270981701; Thu, 24 Sep 2026 10:29:41 -0700 (PDT) Date: Thu, 24 Sep 2026 17:29:15 +0000 In-Reply-To: <20260924172928.2110956-1-coltonlewis@google.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260924172928.2110956-1-coltonlewis@google.com> X-Mailer: git-send-email 2.56.0.rc1.315.gc6ed9934b7-goog Message-ID: <20260924172928.2110956-10-coltonlewis@google.com> Subject: [PATCH v9 09/22] KVM: arm64: Set up FGT for Partitioned PMU From: Colton Lewis To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Oliver Upton , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Fuad Tabba , Catalin Marinas , Will Deacon , Mark Rutland , Paolo Bonzini , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , James Clark , Robin Murphy , Zide Chen , Alexandru Elisei , Ganapatrao Kulkarni , Mingwei Zhang , Jonathan Corbet , Russell King , Shuah Khan , linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Colton Lewis Content-Type: text/plain; charset="UTF-8" In order to gain the best performance benefit from partitioning the PMU, utilize fine grain traps (FEAT_FGT and FEAT_FGT2) to avoid trapping common PMU register accesses by the guest to remove that overhead. Untrapped: - PMCR_EL0 - PMUSERENR_EL0 - PMSELR_EL0 - PMCCNTR_EL0 - PMCNTEN_EL0 - PMINTEN_EL1 - PMEVCNTRn_EL0 These are safe to untrap because writing MDCR_EL2.HPMN as this series will do limits the effect of writes to any of these registers to the partition of counters 0..HPMN-1. Reads from these registers will not leak information from between guests as all these registers are context swapped by a later patch in this series. Reads from these registers also do not leak any information about the host's hardware beyond what is promised by PMUv3. Trapped: - PMOVS_EL0 - PMEVTYPERn_EL0 - PMCCFILTR_EL0 - PMICNTR_EL0 - PMICFILTR_EL0 - PMCEIDn_EL0 - PMMIR_EL1 PMOVS remains trapped so KVM can track overflow IRQs that will need to be injected into the guest. PMICNTR and PMICFILTR remain trapped because KVM is not handling them yet. PMEVTYPERn remains trapped so KVM can limit which events guests can count, such as disallowing counting at EL2. PMCCFILTR and PMICFILTR are special cases of the same. PMCEIDn and PMMIR remain trapped because they can leak information specific to the host hardware implementation. Signed-off-by: Colton Lewis --- arch/arm64/kvm/config.c | 49 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/config.c b/arch/arm64/kvm/config.c index 1053676551aff..f00ef9d598a95 100644 --- a/arch/arm64/kvm/config.c +++ b/arch/arm64/kvm/config.c @@ -1708,12 +1708,55 @@ static void __compute_hfgwtr(struct kvm_vcpu *vcpu) *vcpu_fgt(vcpu, HFGWTR_EL2) |= HFGWTR_EL2_TCR_EL1; } +static void __compute_hdfgrtr(struct kvm_vcpu *vcpu) +{ + __compute_fgt(vcpu, HDFGRTR_EL2); + + if (kvm_pmu_is_partitioned(vcpu->kvm)) { + *vcpu_fgt(vcpu, HDFGRTR_EL2) |= + (HDFGRTR_EL2_PMOVS | + HDFGRTR_EL2_PMCCFILTR_EL0 | + HDFGRTR_EL2_PMEVTYPERn_EL0 | + HDFGRTR_EL2_PMCEIDn_EL0 | + HDFGRTR_EL2_PMMIR_EL1) & ~hdfgrtr_masks.res0; + } +} + static void __compute_hdfgwtr(struct kvm_vcpu *vcpu) { __compute_fgt(vcpu, HDFGWTR_EL2); if (is_hyp_ctxt(vcpu)) *vcpu_fgt(vcpu, HDFGWTR_EL2) |= HDFGWTR_EL2_MDSCR_EL1; + + if (kvm_pmu_is_partitioned(vcpu->kvm)) { + *vcpu_fgt(vcpu, HDFGWTR_EL2) |= + (HDFGWTR_EL2_PMOVS | + HDFGWTR_EL2_PMCCFILTR_EL0 | + HDFGWTR_EL2_PMEVTYPERn_EL0) & ~hdfgwtr_masks.res0; + } +} + +static void __compute_hdfgrtr2(struct kvm_vcpu *vcpu) +{ + __compute_fgt(vcpu, HDFGRTR2_EL2); + + if (kvm_pmu_is_partitioned(vcpu->kvm)) { + *vcpu_fgt(vcpu, HDFGRTR2_EL2) &= + ~(HDFGRTR2_EL2_nPMICFILTR_EL0 | + HDFGRTR2_EL2_nPMICNTR_EL0) | hdfgrtr2_masks.res1; + } +} + +static void __compute_hdfgwtr2(struct kvm_vcpu *vcpu) +{ + __compute_fgt(vcpu, HDFGWTR2_EL2); + + if (kvm_pmu_is_partitioned(vcpu->kvm)) { + *vcpu_fgt(vcpu, HDFGWTR2_EL2) &= + ~(HDFGWTR2_EL2_nPMICFILTR_EL0 | + HDFGWTR2_EL2_nPMICNTR_EL0) | hdfgwtr2_masks.res1; + } } static void __compute_ich_hfgrtr(struct kvm_vcpu *vcpu) @@ -1750,7 +1793,7 @@ void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu) __compute_fgt(vcpu, HFGRTR_EL2); __compute_hfgwtr(vcpu); __compute_fgt(vcpu, HFGITR_EL2); - __compute_fgt(vcpu, HDFGRTR_EL2); + __compute_hdfgrtr(vcpu); __compute_hdfgwtr(vcpu); __compute_fgt(vcpu, HAFGRTR_EL2); @@ -1758,8 +1801,8 @@ void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu) __compute_fgt(vcpu, HFGRTR2_EL2); __compute_fgt(vcpu, HFGWTR2_EL2); __compute_fgt(vcpu, HFGITR2_EL2); - __compute_fgt(vcpu, HDFGRTR2_EL2); - __compute_fgt(vcpu, HDFGWTR2_EL2); + __compute_hdfgrtr2(vcpu); + __compute_hdfgwtr2(vcpu); } if (cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF)) { -- 2.56.0.rc1.310.g51773c2048-goog