Re: [PATCH v2 1/2] perf riscv: Implement rdtsc()

[sashiko-bot@kernel.org]

> Perf has no riscv implementation of rdtsc(), so it links against the weak
> stub in util/tsc.c and every caller reads a constant 0 that cannot be
> told apart from a counter standing still.
> 
> Implement rdtsc() over the time CSR with rdtime.  The time CSR is a TSC
> equivalent on riscv: readable from user mode, constant frequency, and the
> same counter riscv's arch_perf_update_userpage() builds the user page
> conversion fields from, so the counter and perf time share a timebase.
> 
> Define it for RV64 only.  Reading the counter whole on RV32 takes time and
> timeh in a loop, and no RV32 user in tools/perf needs it that much, so
> RV32 keeps the weak stub.
> 
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260929034133.2153-1-cp0613@linux.alibaba.com?part=1