From: sashiko-bot@kernel.org
To: "Himanshu Chauhan" <himanshu.chauhan@oss.qualcomm.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [PATCH v7 2/8] riscv: Add breakpoint and watchpoint test for riscv
Date: Wed, 30 Sep 2026 06:49:56 +0000 [thread overview]
Message-ID: <20260930064957.23FD71F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260930063919.608911-3-himanshu.chauhan@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [Medium] selftests/breakpoints: Makefile fails to match riscv64 native architecture
- [Low] selftests/breakpoints: global CFLAGS += -static affects other tests
- [Low] selftests/breakpoints: file descriptor leak in trigger_wp()
- [Low] selftests/breakpoints: shared variables lack volatile sig_atomic_t qualifier
--
commit d5a08206a858d8d5760badeff5fe2c51c8a98f2b
Author: Himanshu Chauhan <himanshu.chauhan@oss.qualcomm.com>
Subject: riscv: Add breakpoint and watchpoint test for riscv
This commit adds a selftest for the RISC-V architecture using the ptrace
framework. It sets and unsets breakpoints and watchpoints, and uses signals
to verify the triggers.
> diff --git a/tools/testing/selftests/breakpoints/Makefile b/tools/testing/selftests/breakpoints/Makefile
> index 0b8f5acf7c78f..b32c56b3c1db2 100644
> --- a/tools/testing/selftests/breakpoints/Makefile
> +++ b/tools/testing/selftests/breakpoints/Makefile
> @@ -12,5 +12,10 @@ ifneq (,$(filter $(ARCH),aarch64 arm64))
> TEST_GEN_PROGS += breakpoint_test_arm64
> endif
>
> +ifneq (,$(filter $(ARCH),riscv))
[Severity: Medium]
Will this test be silently skipped during a native build on a RISC-V machine?
The native architecture reported by uname -m is "riscv64", but this filter
expects exactly "riscv". Since this leaf Makefile doesn't include the
kernel's subarch.include to normalize the architecture name, it looks like it
might fail to match the native architecture.
> +CFLAGS += -static $(KHDR_INCLUDES)
[Severity: Low]
Does appending to the global CFLAGS here force other unrelated tests in this
directory to inadvertently build statically on RISC-V?
Using a target-specific flag just for breakpoint_test_riscv might prevent
impacting tests like step_after_suspend_test.
> +TEST_GEN_PROGS += breakpoint_test_riscv
> +endif
> +
> include ../lib.mk
[ ... ]
> diff --git a/tools/testing/selftests/breakpoints/breakpoint_test_riscv.c b/tools/testing/selftests/breakpoints/breakpoint_test_riscv.c
> new file mode 100644
> index 0000000000000..0649940b709e0
> --- /dev/null
> +++ b/tools/testing/selftests/breakpoints/breakpoint_test_riscv.c
> @@ -0,0 +1,219 @@
[ ... ]
> +#ifndef noinline
> +#define noinline __attribute__((noinline))
> +#endif
> +
> +static int gfd;
> +sem_t ib_mtx, wp_mtx;
> +static int bp_triggered, wp_triggered;
[Severity: Low]
Can the compiler optimize and incorrectly cache these variables since they
are modified asynchronously in a signal handler but lack the volatile
sig_atomic_t qualifiers?
They are incremented in sig_handler_bp() and sig_handler_wp(), so standard
POSIX signal safety might require the proper qualifiers to avoid potential
hangs or incorrect test failures.
> +static int test_func_sink;
> +static const int wait_timeout_sec = 5;
[ ... ]
> +static int trigger_wp(void)
> +{
> + struct sigaction sa;
> + unsigned long test_data;
[ ... ]
> + if (gfd < 0) {
> + printf("Failed to setup watchpoint\n");
> + return -1;
> + }
> +
> + ioctl(gfd, PERF_EVENT_IOC_ENABLE, 0);
> + test_data = 0xdeadbeef;
> + ioctl(gfd, PERF_EVENT_IOC_DISABLE, 0);
> +
> + return 0;
> +}
[Severity: Low]
Does this success path leak the file descriptor allocated by setup_bp()?
It looks like close(gfd) is correctly called on the success path in
trigger_bp(), but appears to be missing here before returning.
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260930063919.608911-1-himanshu.chauhan@oss.qualcomm.com?part=2
next prev parent reply other threads:[~2026-09-30 6:49 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-30 6:39 [PATCH v7 0/8] riscv: Introduce support for hardware break/watchpoints Himanshu Chauhan
2026-09-30 6:39 ` [PATCH v7 1/8] " Himanshu Chauhan
2026-09-30 6:58 ` sashiko-bot
2026-09-30 6:39 ` [PATCH v7 2/8] riscv: Add breakpoint and watchpoint test for riscv Himanshu Chauhan
2026-09-30 6:49 ` sashiko-bot [this message]
2026-09-30 6:39 ` [PATCH v7 3/8] riscv: ptrace support for hardware break/watchpoints Himanshu Chauhan
2026-09-30 6:56 ` sashiko-bot
2026-09-30 6:39 ` [PATCH v7 4/8] selftests/breakpoints: extend riscv test for ptrace hw break/watchpoints Himanshu Chauhan
2026-09-30 6:51 ` sashiko-bot
2026-09-30 6:39 ` [PATCH v7 5/8] RISC-V: Add fetch and decode helpers to a common file Himanshu Chauhan
2026-09-30 6:50 ` sashiko-bot
2026-09-30 6:39 ` [PATCH v7 6/8] riscv: Add software supported single stepping with mc/mc6 triggers Himanshu Chauhan
2026-09-30 6:56 ` sashiko-bot
2026-09-30 6:39 ` [PATCH v7 7/8] perf tests: add noinline to __test_function Himanshu Chauhan
2026-09-30 6:45 ` sashiko-bot
2026-09-30 6:39 ` [PATCH v7 8/8] MAINTAINERS: Add entry for RISC-V Debugging Himanshu Chauhan
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