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Wed, 21 Oct 2026 15:45:45 -0700 (PDT) Received: from a1-free ([161.33.196.121]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36740cc88b5sm10770274eec.10.2026.10.21.15.45.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 15:45:44 -0700 (PDT) From: TAKANO Mitsuhiro To: linux-perf-users@vger.kernel.org, Arnaldo Carvalho de Melo Cc: Namhyung Kim , Ian Rogers , Ilkka Koskinen , John Garry , TAKANO Mitsuhiro Subject: [PATCH] perf vendor events arm64 AmpereOneX: Drop stale BPU_FLUSH_MEM_FAULT entry Date: Wed, 21 Oct 2026 22:45:27 +0000 Message-ID: <20261021224527.167637-1-takano32@gmail.com> X-Mailer: git-send-email 2.53.0 X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit AmpereOne carried BPU_FLUSH_MEM_FAULT for EventCode 0x121 until it was renamed to GPC_FLUSH_MEM_FAULT in 10a149e4b4a9; that rename and the AmpereOneX table were patches 3 and 4 of the same series, so the new file kept the old name. The result is a table that names the 0x121 counter twice: ampereonex/core-imp-def.json has GPC_FLUSH_MEM_FAULT, and ampereonex/memory.json adds BPU_FLUSH_MEM_FAULT with the same code and the same description. On AmpereOneX perf therefore lists two events for one counter, one of them under a name the documentation does not use. No metric and no other file refers to either name, so removing the stale entry cannot change a metric. It also leaves memory.json holding only the ArchStdEvent aliases the other files of that kind carry: AmpereOne's memory.json has no raw EventCode at all, and neither has any other file of the AmpereOneX set except the ones where raw codes belong. Nothing catches this at build time. jevents.py asserts on duplicate event names, but x86 repeats an EventCode for many events because the code carries umask and unit bits (3756 times across its tables) and powerpc repeats five codes, so a duplicate-code check is not possible. arm64 is the only architecture where no table but this one repeats a code. Not tested on hardware: there is no AmpereOneX machine here, so perf was not run against the real PMU. The change only edits a JSON table; the perf build was verified and the generated table for this PMU goes from two names for 0x121 to one (rebuilt, counted in pmu-events.c). Fixes: 16438b652b46 ("perf vendor events arm64 AmpereOneX: Add core PMU events and metrics") Assisted-by: LLM Signed-off-by: TAKANO Mitsuhiro --- .../pmu-events/arch/arm64/ampere/ampereonex/memory.json | 6 ------ 1 file changed, 6 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/memory.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/memory.json index 6c06bc928415..2a83782f51b0 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/memory.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/memory.json @@ -33,11 +33,5 @@ }, { "ArchStdEvent": "MEM_ACCESS_CHECKED_WR" - }, - { - "PublicDescription": "Flushes due to memory hazards", - "EventCode": "0x121", - "EventName": "BPU_FLUSH_MEM_FAULT", - "BriefDescription": "Flushes due to memory hazards" } ] base-commit: f47d223627f80cb7a1eb14c585fe6cb35de5e984 -- 2.53.0