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Sun, 01 Nov 2026 11:28:15 -0800 (PST) Received: from localhost ([2600:1702:7a90:6f9f:8bc4:8aec:108d:7a04]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-67baf147246sm3725582d50.1.2026.11.01.11.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Nov 2026 11:28:13 -0800 (PST) From: Matt Turner Date: Sun, 01 Nov 2026 14:28:07 -0500 Subject: [PATCH v3 4/7] alpha/perf: do not report user registers from the entry code X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261101-alpha-profileme-v3-4-92d511b5a044@gmail.com> References: <20261101-alpha-profileme-v3-0-92d511b5a044@gmail.com> In-Reply-To: <20261101-alpha-profileme-v3-0-92d511b5a044@gmail.com> To: Richard Henderson , Magnus Lindholm , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Oleg Nesterov Cc: linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Matt Turner , Peter Zijlstra , Ingo Molnar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3729; i=mattst88@gmail.com; h=from:subject:message-id; bh=j745NTzeMTR18QqhA7qldpQHNflfi9v6N9g1RNlRzvQ=; b=owGbwMvMwCW25rVmCc8sv+mMp9WSGLKeTzq6Sl6wf26HPOuy6bzXHd/tkyo+EHgquN/4dgbXx etrG5qOd3xkYRDjYpgppsgSt16RZVbbjqU+p6V/wcxhZQIZIi3SwAAELAx8uYl5pUY6Rnqm2oZ6 hkCGjlE8RE6PQSOzuLg0tUg3raDIIS+/JLEkMz+vWC+/IDWvIL1ALy0zrSQjI7+oOBVohF5eaom pq6ObkaGBiaWjhZmThaOpibOzk6GTm6Ojs6uTkaW5iYGzpaOJq6U5AxenAMw1H/gYGd7PV7JjWs H7R3lnVdoMNTZlm/DZc8vvn/8x377pzI+F/bGMDCs2y6y8+d59Wvelf+ufMVVo/J6XLLKPVfHsk rnr5Y71ybEAAA== X-Developer-Key: i=mattst88@gmail.com; a=openpgp; fpr=3BB639E56F861FA2E86505690FDD682D974CA72A perf_get_regs_user() returns task_pt_regs() whenever a sample of a user task lands in the kernel. But exception entry runs with interrupts enabled, so the sample can land before the entry code has saved the user registers. Only the part PALcode pushed is valid then. An interrupt taken on the first instruction of entUna, say, pushes its own frame on top of PALcode's, which overlaps the rest of the user frame, so r7 and r8 read as the interrupt's r23 and r24. Report no user registers while the interrupted PC is in the entry code. Such a sample also gets no user stack dump. The range is all of the entry code from entInt to the end of the save in entSys, so it also drops the registers of samples that land after they were saved there. An interrupt that nests on one taken in the entry code still reads the incomplete frame, as its own PC has left the entry code. Fixes: 9280e99d87dd ("alpha: add HAVE_PERF_REGS and HAVE_PERF_USER_STACK_DUMP support") Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Matt Turner --- arch/alpha/include/asm/ptrace.h | 12 ++++++++++++ arch/alpha/kernel/entry.S | 8 ++++++++ arch/alpha/kernel/perf_regs.c | 13 +++++++++++++ 3 files changed, 33 insertions(+) diff --git a/arch/alpha/include/asm/ptrace.h b/arch/alpha/include/asm/ptrace.h index 45d1229344b6..1400ba3e7d43 100644 --- a/arch/alpha/include/asm/ptrace.h +++ b/arch/alpha/include/asm/ptrace.h @@ -14,6 +14,18 @@ #define task_pt_regs(task) \ ((struct pt_regs *) (task_stack_page(task) + 2*PAGE_SIZE) - 1) +/* + * Whether pc is in entry code that may not have completed the frame at + * task_pt_regs(). See entry.S. + */ +static inline bool in_entry_save_code(unsigned long pc) +{ + extern char __entry_save_start[], __entry_save_end[]; + + return pc >= (unsigned long)__entry_save_start && + pc < (unsigned long)__entry_save_end; +} + #define current_pt_regs() \ ((struct pt_regs *) ((char *)current_thread_info() + 2*PAGE_SIZE) - 1) diff --git a/arch/alpha/kernel/entry.S b/arch/alpha/kernel/entry.S index 790389a15c3c..2de7cdd3a872 100644 --- a/arch/alpha/kernel/entry.S +++ b/arch/alpha/kernel/entry.S @@ -186,8 +186,14 @@ /* * Non-syscall kernel entry points. + * + * Between __entry_save_start and __entry_save_end the frame at task_pt_regs() + * may not be complete. perf uses these to avoid reading it. */ + .globl __entry_save_start +__entry_save_start: + CFI_START_OSF_FRAME entInt SAVE_ALL lda $8, 0x3fff @@ -473,6 +479,8 @@ CFI_END_OSF_FRAME entDbg .cfi_rel_offset $gp, 16 entSys: SAVE_ALL + .globl __entry_save_end +__entry_save_end: ldq $1, 0($sp) /* syscall nr from saved r0 */ stq $1, 8($sp) /* regs->r1 = shadow syscall nr */ diff --git a/arch/alpha/kernel/perf_regs.c b/arch/alpha/kernel/perf_regs.c index 33ea2e831ba0..894683851b30 100644 --- a/arch/alpha/kernel/perf_regs.c +++ b/arch/alpha/kernel/perf_regs.c @@ -59,6 +59,19 @@ u64 perf_reg_abi(struct task_struct *task) void perf_get_regs_user(struct perf_regs *regs_user, struct pt_regs *regs) { + /* + * Exception entry runs with interrupts enabled, so a sample can land + * before the entry code has saved the user registers. PALcode has + * pushed only its part of the frame, and the rest may hold an + * interrupt's frame. An interrupt that nests on top of one taken here + * is not caught, as its PC has left the entry code. + */ + if (in_entry_save_code(regs->pc)) { + regs_user->regs = NULL; + regs_user->abi = PERF_SAMPLE_REGS_ABI_NONE; + return; + } + regs_user->regs = task_pt_regs(current); regs_user->abi = perf_reg_abi(current); } -- 2.55.0