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Thu, 12 Nov 2026 11:09:27 -0800 (PST) Received: from eldorado ([2600:8802:b00:1f88::287]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-37956bad6casm395674eec.26.2026.11.12.11.09.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 11:09:26 -0800 (PST) From: Florian Fainelli To: linux-mips@vger.kernel.org Cc: Florian Fainelli , Thomas Bogendoerfer , Jonathan Corbet , Shuah Khan , Randy Dunlap , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Thomas Gleixner , linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-kernel@vger.kernel.org (open list), linux-perf-users@vger.kernel.org (open list:PERFORMANCE EVENTS SUBSYSTEM), "Maciej W. Rozycki" Subject: [PATCH 1/3] MIPS: SiByte: Wire up the CPU interrupt controller Date: Thu, 12 Nov 2026 11:09:14 -0800 Message-ID: <20261112190916.3725141-2-f.fainelli@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261112190916.3725141-1-f.fainelli@gmail.com> References: <20261112190916.3725141-1-f.fainelli@gmail.com> X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Initialize the MIPS CPU interrupt controller on SB1250 and BCM1480 so CPU-local interrupts have a configured irq_chip and handler. Reserve IRQs 128 through 135 above both interrupt mapper ranges, and dispatch BCM1480 IP7 through the CPU controller as SB1250 already does. This provides the CPU-local IP7 interrupt needed by the SB1 performance counters without overlapping the SiByte interrupt mapper IRQ numbers. Signed-off-by: Florian Fainelli --- arch/mips/include/asm/mach-sibyte/irq.h | 10 ++++++++++ arch/mips/sibyte/bcm1480/irq.c | 7 ++++++- arch/mips/sibyte/sb1250/irq.c | 3 +++ 3 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 arch/mips/include/asm/mach-sibyte/irq.h diff --git a/arch/mips/include/asm/mach-sibyte/irq.h b/arch/mips/include/asm/mach-sibyte/irq.h new file mode 100644 index 000000000000..b7073830d2ec --- /dev/null +++ b/arch/mips/include/asm/mach-sibyte/irq.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_MACH_SIBYTE_IRQ_H +#define __ASM_MACH_SIBYTE_IRQ_H + +/* Keep CPU-local interrupts above both SiByte interrupt mapper ranges. */ +#define MIPS_CPU_IRQ_BASE 128 + +#include + +#endif diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index 4c18a2c755d2..5eff85a8659b 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -242,6 +243,8 @@ void __init arch_init_irq(void) unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | STATUSF_IP1 | STATUSF_IP0; + mips_cpu_irq_init(); + /* Default everything to IP2 */ /* Start with _high registers which has no bit 0 interrupt source */ for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */ @@ -337,7 +340,9 @@ asmlinkage void plat_irq_dispatch(void) pending = read_c0_cause() & read_c0_status(); - if (pending & CAUSEF_IP4) + if (pending & CAUSEF_IP7) + do_IRQ(MIPS_CPU_IRQ_BASE + 7); + else if (pending & CAUSEF_IP4) do_IRQ(K_BCM1480_INT_TIMER_0 + cpu); #ifdef CONFIG_SMP else if (pending & CAUSEF_IP3) diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 57943fe3ac03..2df115269f81 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -225,6 +226,8 @@ void __init arch_init_irq(void) unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | STATUSF_IP1 | STATUSF_IP0; + mips_cpu_irq_init(); + /* Default everything to IP2 */ for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ __raw_writeq(IMR_IP2_VAL, -- 2.53.0