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Thu, 12 Nov 2026 14:45:15 -0800 (PST) Received: from ryzen.lan ([2601:644:8000:37f::e34]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b1b3b708adsm37073a91.4.2026.11.12.14.45.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 14:45:13 -0800 (PST) From: Rosen Penev To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Thomas Bogendoerfer , Thomas Gleixner Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Radu Rendec , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 4/4] irqchip/ath79-misc: allow COMPILE_TEST builds Date: Thu, 12 Nov 2026 14:44:45 -0800 Message-ID: <20261112224445.213324-5-rosenp@gmail.com> X-Mailer: git-send-email 2.56.1 In-Reply-To: <20261112224445.213324-1-rosenp@gmail.com> References: <20261112224445.213324-1-rosenp@gmail.com> X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The driver is only built with ATH79, so only ath79 kernels build it. As a platform driver, its only MIPS-specific parts are the performance counter hook and the call to spurious_interrupt(). Add a Kconfig symbol that defaults to ATH79 and can be enabled with COMPILE_TEST. Build the performance counter hook only with ATH79, as other MIPS platforms provide their own. Drop the call to spurious_interrupt(), which only exists on MIPS: a cascaded interrupt with nothing pending only bumped the error count in /proc/interrupts, and the handler now just returns. Signed-off-by: Rosen Penev --- drivers/irqchip/Kconfig | 14 ++++++++++++++ drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-ath79-misc.c | 19 ++++++++++++------- 3 files changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 731041def5d6..91fcc433afab 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -127,6 +127,20 @@ config ASPEED_AST2700_INTC_TEST If unsure, say N. +config ATH79_MISC_IRQ + bool "Atheros/Qualcomm ath79 MISC interrupt controller" if COMPILE_TEST + depends on ATH79 || COMPILE_TEST + depends on OF + depends on HAS_IOMEM + default ATH79 + select IRQ_DOMAIN + help + Support the MISC interrupt controller of the Atheros/Qualcomm + ath79 SoCs. It is cascaded from a CPU interrupt and collects the + interrupts of the UART, GPIO, timers, watchdog and performance + counters, among others. It is enabled by default on ath79, and + only needs to be selected by hand for compile testing. + config ATMEL_AIC_IRQ bool select GENERIC_IRQ_CHIP diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 16a5fd126c9a..de7be9803c74 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -4,7 +4,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o obj-$(CONFIG_AL_FIC) += irq-al-fic.o obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o obj-$(CONFIG_ATH79) += irq-ath79-cpu.o -obj-$(CONFIG_ATH79) += irq-ath79-misc.o +obj-$(CONFIG_ATH79_MISC_IRQ) += irq-ath79-misc.o obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o diff --git a/drivers/irqchip/irq-ath79-misc.c b/drivers/irqchip/irq-ath79-misc.c index b06ece446746..dc865dbbbc3b 100644 --- a/drivers/irqchip/irq-ath79-misc.c +++ b/drivers/irqchip/irq-ath79-misc.c @@ -16,7 +16,9 @@ #include #include +#ifdef CONFIG_ATH79 #include +#endif #define AR71XX_RESET_REG_MISC_INT_STATUS 0 #define AR71XX_RESET_REG_MISC_INT_ENABLE 4 @@ -24,8 +26,14 @@ #define ATH79_MISC_IRQ_COUNT 32 #define ATH79_MISC_PERF_IRQ 5 +#ifdef CONFIG_ATH79 static struct irq_domain *ath79_misc_domain; +static void ath79_misc_set_perf_domain(struct irq_domain *domain) +{ + ath79_misc_domain = domain; +} + /* Called by the MIPS perf code when the first event is created. */ int get_c0_perfcount_int(void) { @@ -39,6 +47,9 @@ int get_c0_perfcount_int(void) return irq ? irq : -1; } EXPORT_SYMBOL_GPL(get_c0_perfcount_int); +#else +static void ath79_misc_set_perf_domain(struct irq_domain *domain) { } +#endif static void ath79_misc_irq_handler(struct irq_desc *desc) { @@ -52,12 +63,6 @@ static void ath79_misc_irq_handler(struct irq_desc *desc) pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); - if (!pending) { - spurious_interrupt(); - chained_irq_exit(chip, desc); - return; - } - while (pending) { int bit = __ffs(pending); @@ -151,7 +156,7 @@ static int ath79_misc_intc_probe(struct platform_device *pdev) __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain); - ath79_misc_domain = domain; + ath79_misc_set_perf_domain(domain); return 0; } -- 2.56.1