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Fri, 13 Nov 2026 15:34:06 -0800 (PST) Received: from eldorado ([2600:8802:b00:1f88::287]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-379553316f2sm10726041eec.9.2026.11.13.15.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 15:34:05 -0800 (PST) From: Florian Fainelli To: linux-mips@vger.kernel.org Cc: Florian Fainelli , Thomas Bogendoerfer , Jonathan Corbet , Shuah Khan , Randy Dunlap , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Thomas Gleixner , linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-kernel@vger.kernel.org (open list), linux-perf-users@vger.kernel.org (open list:PERFORMANCE EVENTS SUBSYSTEM), "Maciej W. Rozycki" Subject: [PATCH v2 0/3] MIPS: SiByte: Add HW PMU support Date: Fri, 13 Nov 2026 15:33:53 -0800 Message-ID: <20261113233358.538698-1-f.fainelli@gmail.com> X-Mailer: git-send-email 2.53.0 X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch series resurrects the SiByte HW PMU support which used to be supported with oprofile but was later removed. Changes in v2: • Preserve usercopy fault state during callchain unwinding. Save and restore current->thread.cp0_baduaddr so faulting unwinder reads cannot corrupt an interrupted usercopy’s recovery • Balance PMU event initialization cleanup. Release resources exactly once on initialization failure and install the destroy callback only on success. Also check event type before rejecting unsupported attributes, allowing unrelated events to fall back to another PMU • Keep disabled PMU interrupts masked after EOI. Add an SB1 IRQ flow wrapper that reapplies the mask when interrupt work disables the last event; the generic CPU IRQ EOI would otherwise unmask IP7 again • Fix a documentation heading underline in sb1-pmu.rst (Randy, sashiko) Florian Fainelli (3): MIPS: SiByte: Wire up the CPU interrupt controller MIPS: perf: Add SB1 userspace callchain unwinding MIPS: perf: Add SB1 and SB1A performance counter support Documentation/arch/mips/index.rst | 1 + Documentation/arch/mips/sb1-pmu.rst | 162 ++++++++++ arch/mips/include/asm/mach-sibyte/irq.h | 10 + arch/mips/kernel/perf_event.c | 110 ++++++- arch/mips/kernel/perf_event_mipsxx.c | 397 ++++++++++++++++++++++-- arch/mips/sibyte/bcm1480/irq.c | 7 +- arch/mips/sibyte/sb1250/irq.c | 3 + include/linux/cpuhotplug.h | 1 + 8 files changed, 666 insertions(+), 25 deletions(-) create mode 100644 Documentation/arch/mips/sb1-pmu.rst create mode 100644 arch/mips/include/asm/mach-sibyte/irq.h -- 2.53.0