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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YKscR3mnIUO9OE6RTn7JgfzpwpN75Rxn2SOZ/nlrQNs38mXsqovbQnMzPk5ZqfeRAdVN7QbS+n4D2KeU/NqBJs95/z8cYKM7cHXXG4XyCx6dkz2g8syVAKNQdoUotPZPI2eM7VgfkMIdaMsGItmAI4WYBaU3Nu4SDDAmFHlvB5kmhBJUhcOi3wtIqi5FOnmYttjPunW2NdnYZmkApD7DnsGCi5HngluYV4BKVPnlwHBW16V5Z7I9Ha+H8W9cmjBOIfgKLpEFpbZwca7upHCmaXzgcySxegEQfRpvS3+MRyHCyZ5EZ9SKrn7cKd0fDTbM0tuoMjRRst8z4lS/liTbPgyyo8KYlGGoUd9HGQOVlNLPMh0pxbMeJ30EWhr/4G7dW8l8Sx7JtTBz2K12QvUjjFbxYNoHZv4EkKVsICcExEVrYP6GqsBMt46JrtbYteZQ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2026 05:05:13.7864 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2eb9538-e908-40c2-9f44-08df071d70d8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000C6195.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5631 >>> 2. perf: precise events and DWARF call graphs are mutually exclusive on this >>> hardware, so arguably perf should simply not let the two be combined. I >>> would suggest two rules rather than one, because a blanket refusal would >>> make the common case worse: >>> >>> - for the default event, drop the P when --call-graph dwarf is requested, >>> silently and on PMUs where precision means IBS. Otherwise a plain >>> "perf record -g --call-graph dwarf" starts failing outright on every AMD >>> box, which is worse than today. The s390 case in evlist.c suggests this >>> kind of substitution is considered acceptable; >>> >>> - if the user asked for a precise event explicitly and also asked for >>> DWARF call chains, refuse with a message that says why and what to do, >>> instead of quietly producing a useless result. >>> >>> Note that this should be scoped to IBS. On Intel, PEBS records the whole >>> register set, so precise events and DWARF unwinding work together there >>> and nothing needs restricting. Frame-pointer call graphs are also fine >>> with precise events - only the leaf frame is off. >> >> I think we can enable both precise IP and dwarf callchains by using >> PERF_SAMPLE_REGS_INTR. For unwinding, it should use PERF_REG_X86_IP >> from the REGS_INTR instead of sample.ip > > Ok, it seems we already do this in the perf tools but it looks like the > kernel already overwrote the PERF_REG_X86_IP with the precise IP. I > feel like we should fix the kernel. This should resolve the DWARF unwinding issue with IBS PMUs: --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1523,8 +1523,11 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) goto out; } - set_linear_ip(®s, ibs_data.regs[1]); - regs.flags |= PERF_EFLAGS_EXACT; + if (event->attr.sample_type & PERF_SAMPLE_IP) { + data.ip = ibs_data.regs[1]; + data.sample_flags |= PERF_SAMPLE_IP; + regs.flags |= PERF_EFLAGS_EXACT; + } } if (((ibs_caps & IBS_CAPS_BIT63_FILTER) || --- However, there's no way to address the stack being out of sync with the IBS RIP, since the IBS HW does not capture GPRs alongside the sample. Thanks, Ravi