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X-CSE-ConnectionGUID: iLvwjikqTRyX0UjHI+YP+g== X-CSE-MsgGUID: TZolH5mnSKeA/UZgTdQrYQ== X-IronPort-AV: E=McAfee;i="6800,10657,11635"; a="77431380" X-IronPort-AV: E=Sophos;i="6.20,258,1758610800"; d="scan'208";a="77431380" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2025 21:24:55 -0800 X-CSE-ConnectionGUID: lN2N9BaiRT+SrG+gFzoTeQ== X-CSE-MsgGUID: ntuZ6btuRQyRSNjcG0D9aQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,258,1758610800"; d="scan'208";a="233215898" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.240.12]) ([10.124.240.12]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2025 21:24:50 -0800 Message-ID: <288614cf-d22f-4329-8440-5a3ab7299041@linux.intel.com> Date: Mon, 8 Dec 2025 13:24:47 +0800 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [Patch v5 07/19] perf: Add sampling support for SIMD registers To: Peter Zijlstra Cc: Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Thomas Gleixner , Dave Hansen , Ian Rogers , Adrian Hunter , Jiri Olsa , Alexander Shishkin , Andi Kleen , Eranian Stephane , Mark Rutland , broonie@kernel.org, Ravi Bangoria , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Kan Liang References: <20251203065500.2597594-1-dapeng1.mi@linux.intel.com> <20251203065500.2597594-8-dapeng1.mi@linux.intel.com> <20251205110706.GT2528459@noisy.programming.kicks-ass.net> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20251205110706.GT2528459@noisy.programming.kicks-ass.net> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 12/5/2025 7:07 PM, Peter Zijlstra wrote: > On Wed, Dec 03, 2025 at 02:54:48PM +0800, Dapeng Mi wrote: > >> @@ -545,6 +547,25 @@ struct perf_event_attr { >> __u64 sig_data; >> >> __u64 config3; /* extension of config2 */ >> + >> + >> + /* >> + * Defines set of SIMD registers to dump on samples. >> + * The sample_simd_regs_enabled !=0 implies the >> + * set of SIMD registers is used to config all SIMD registers. >> + * If !sample_simd_regs_enabled, sample_regs_XXX may be used to >> + * config some SIMD registers on X86. >> + */ >> + union { >> + __u16 sample_simd_regs_enabled; >> + __u16 sample_simd_pred_reg_qwords; >> + }; >> + __u32 sample_simd_pred_reg_intr; >> + __u32 sample_simd_pred_reg_user; >> + __u16 sample_simd_vec_reg_qwords; >> + __u64 sample_simd_vec_reg_intr; >> + __u64 sample_simd_vec_reg_user; >> + __u32 __reserved_4; >> }; > This is poorly aligned and causes holes. > > This: > > diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h > index d292f96bc06f..2deb8dd0ca37 100644 > --- a/include/uapi/linux/perf_event.h > +++ b/include/uapi/linux/perf_event.h > @@ -545,6 +545,14 @@ struct perf_event_attr { > __u64 sig_data; > > __u64 config3; /* extension of config2 */ > + > + __u16 sample_simd_pred_reg_qwords; > + __u32 sample_simd_pred_reg_intr; > + __u32 sample_simd_pred_reg_user; > + __u16 sample_simd_vec_reg_qwords; > + __u64 sample_simd_vec_reg_intr; > + __u64 sample_simd_vec_reg_user; > + __u32 __reserved_4; > }; > > /* > > results in: > > __u64 config3; /* 128 8 */ > __u16 sample_simd_pred_reg_qwords; /* 136 2 */ > > /* XXX 2 bytes hole, try to pack */ > > __u32 sample_simd_pred_reg_intr; /* 140 4 */ > __u32 sample_simd_pred_reg_user; /* 144 4 */ > __u16 sample_simd_vec_reg_qwords; /* 148 2 */ > > /* XXX 2 bytes hole, try to pack */ > > __u64 sample_simd_vec_reg_intr; /* 152 8 */ > __u64 sample_simd_vec_reg_user; /* 160 8 */ > __u32 __reserved_4; /* 168 4 */ > > > > A better layout might be: > > diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h > index d292f96bc06f..f72707e9df68 100644 > --- a/include/uapi/linux/perf_event.h > +++ b/include/uapi/linux/perf_event.h > @@ -545,6 +545,15 @@ struct perf_event_attr { > __u64 sig_data; > > __u64 config3; /* extension of config2 */ > + > + __u16 sample_simd_pred_reg_qwords; > + __u16 sample_simd_vec_reg_qwords; > + __u32 __reserved_4; > + > + __u32 sample_simd_pred_reg_intr; > + __u32 sample_simd_pred_reg_user; > + __u64 sample_simd_vec_reg_intr; > + __u64 sample_simd_vec_reg_user; > }; > > /* > > such that: > > __u64 config3; /* 128 8 */ > __u16 sample_simd_pred_reg_qwords; /* 136 2 */ > __u16 sample_simd_vec_reg_qwords; /* 138 2 */ > __u32 __reserved_4; /* 140 4 */ > __u32 sample_simd_pred_reg_intr; /* 144 4 */ > __u32 sample_simd_pred_reg_user; /* 148 4 */ > __u64 sample_simd_vec_reg_intr; /* 152 8 */ > __u64 sample_simd_vec_reg_user; /* 160 8 */ > Sure. Thanks. >