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X-CSE-ConnectionGUID: gwLeiXQ6RlGXcEbNUzqg1Q== X-CSE-MsgGUID: wAZx6V/kQTOKhRz2aHhRbg== X-IronPort-AV: E=McAfee;i="6600,9927,11066"; a="22369867" X-IronPort-AV: E=Sophos;i="6.08,144,1712646000"; d="scan'208";a="22369867" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2024 20:44:18 -0700 X-CSE-ConnectionGUID: DOfKS6+qRf2BYPrgYcoSkA== X-CSE-MsgGUID: BB0qfzbsQo+56jUI7x+SQw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,144,1712646000"; d="scan'208";a="33572091" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.225.92]) ([10.124.225.92]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2024 20:44:12 -0700 Message-ID: <2c4f53fe-0b6f-4e4c-a99c-f1a28677ebf9@linux.intel.com> Date: Wed, 8 May 2024 11:44:10 +0800 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 12/54] perf: x86: Add x86 function to switch PMI handler To: "Chen, Zide" , Mingwei Zhang , Sean Christopherson , Paolo Bonzini , Xiong Zhang , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , maobibo , Like Xu , Peter Zijlstra , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org References: <20240506053020.3911940-1-mizhang@google.com> <20240506053020.3911940-13-mizhang@google.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/8/2024 5:40 AM, Chen, Zide wrote: > > On 5/5/2024 10:29 PM, Mingwei Zhang wrote: >> From: Xiong Zhang >> >> Add x86 specific function to switch PMI handler since passthrough PMU and host >> PMU use different interrupt vectors. >> >> x86_perf_guest_enter() switch PMU vector from NMI to KVM_GUEST_PMI_VECTOR, >> and guest LVTPC_MASK value should be reflected onto HW to indicate whether >> guest has cleared LVTPC_MASK or not, so guest lvt_pc is passed as parameter. >> >> x86_perf_guest_exit() switch PMU vector from KVM_GUEST_PMI_VECTOR to NMI. >> >> Signed-off-by: Xiong Zhang >> Signed-off-by: Dapeng Mi >> --- >> arch/x86/events/core.c | 17 +++++++++++++++++ >> arch/x86/include/asm/perf_event.h | 3 +++ >> 2 files changed, 20 insertions(+) >> >> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c >> index 09050641ce5d..8167f2230d3a 100644 >> --- a/arch/x86/events/core.c >> +++ b/arch/x86/events/core.c >> @@ -701,6 +701,23 @@ struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data) >> } >> EXPORT_SYMBOL_GPL(perf_guest_get_msrs); >> >> +void x86_perf_guest_enter(u32 guest_lvtpc) >> +{ >> + lockdep_assert_irqs_disabled(); >> + >> + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_GUEST_PMI_VECTOR | >> + (guest_lvtpc & APIC_LVT_MASKED)); > If CONFIG_KVM is not defined, KVM_GUEST_PMI_VECTOR is not available and > it causes compiling error. Zide, thanks. If CONFIG_KVM is not defined, these two helpers would not need to be called, it can be defined as null.