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X-CSE-ConnectionGUID: cfAc+qvtTGGpOIeQh2NVBA== X-CSE-MsgGUID: Tem6lO/ATnyuIjhaMsbA0Q== X-IronPort-AV: E=McAfee;i="6600,9927,11066"; a="22144486" X-IronPort-AV: E=Sophos;i="6.08,144,1712646000"; d="scan'208";a="22144486" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2024 23:58:39 -0700 X-CSE-ConnectionGUID: 0BkwCdbAQFyPZLF6xV6Bvg== X-CSE-MsgGUID: R0sjFcOkSfSkgaWarwRK7A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,144,1712646000"; d="scan'208";a="28760747" Received: from tiesheng-mobl.ccr.corp.intel.com (HELO [10.124.225.233]) ([10.124.225.233]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2024 23:58:34 -0700 Message-ID: <34245468-00fc-49aa-951e-d7d786084d08@linux.intel.com> Date: Wed, 8 May 2024 14:58:30 +0800 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 12/54] perf: x86: Add x86 function to switch PMI handler To: Peter Zijlstra , Mingwei Zhang Cc: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das , Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , maobibo , Like Xu , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org References: <20240506053020.3911940-1-mizhang@google.com> <20240506053020.3911940-13-mizhang@google.com> <20240507092241.GV40213@noisy.programming.kicks-ass.net> Content-Language: en-US From: "Zhang, Xiong Y" In-Reply-To: <20240507092241.GV40213@noisy.programming.kicks-ass.net> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/7/2024 5:22 PM, Peter Zijlstra wrote: > On Mon, May 06, 2024 at 05:29:37AM +0000, Mingwei Zhang wrote: >> From: Xiong Zhang >> >> Add x86 specific function to switch PMI handler since passthrough PMU and host >> PMU use different interrupt vectors. >> >> x86_perf_guest_enter() switch PMU vector from NMI to KVM_GUEST_PMI_VECTOR, >> and guest LVTPC_MASK value should be reflected onto HW to indicate whether >> guest has cleared LVTPC_MASK or not, so guest lvt_pc is passed as parameter. >> >> x86_perf_guest_exit() switch PMU vector from KVM_GUEST_PMI_VECTOR to NMI. >> >> Signed-off-by: Xiong Zhang >> Signed-off-by: Dapeng Mi >> --- >> arch/x86/events/core.c | 17 +++++++++++++++++ >> arch/x86/include/asm/perf_event.h | 3 +++ >> 2 files changed, 20 insertions(+) >> >> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c >> index 09050641ce5d..8167f2230d3a 100644 >> --- a/arch/x86/events/core.c >> +++ b/arch/x86/events/core.c >> @@ -701,6 +701,23 @@ struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data) >> } >> EXPORT_SYMBOL_GPL(perf_guest_get_msrs); >> >> +void x86_perf_guest_enter(u32 guest_lvtpc) >> +{ >> + lockdep_assert_irqs_disabled(); >> + >> + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_GUEST_PMI_VECTOR | >> + (guest_lvtpc & APIC_LVT_MASKED)); >> +} >> +EXPORT_SYMBOL_GPL(x86_perf_guest_enter); >> + >> +void x86_perf_guest_exit(void) >> +{ >> + lockdep_assert_irqs_disabled(); >> + >> + apic_write(APIC_LVTPC, APIC_DM_NMI); >> +} >> +EXPORT_SYMBOL_GPL(x86_perf_guest_exit); > > Urgghh... because it makes sense for this bare APIC write to be exported > ?!? Usually KVM doesn't access HW except vmx directly and requests other components to access HW to avoid confliction, APIC_LVTPC is managed by x86 perf driver, so I added two functions here and exported them. > > Can't this at the very least be hard tied to perf_guest_{enter,exit}() ? > perf_guest_{enter, exit} is called from this function in another commit, I should merge that commit into this one according to your suggestion in other email. thanks