From: Kim Phillips <kim.phillips@amd.com>
To: Ravi Bangoria <ravi.bangoria@amd.com>,
peterz@infradead.org, acme@kernel.org
Cc: jolsa@kernel.org, namhyung@kernel.org, eranian@google.com,
irogers@google.com, jmario@redhat.com, leo.yan@linaro.org,
alisaidi@amazon.com, ak@linux.intel.com,
kan.liang@linux.intel.com, dave.hansen@linux.intel.com,
hpa@zytor.com, mingo@redhat.com, mark.rutland@arm.com,
alexander.shishkin@linux.intel.com, tglx@linutronix.de,
bp@alien8.de, x86@kernel.org, linux-perf-users@vger.kernel.org,
linux-kernel@vger.kernel.org, sandipan.das@amd.com,
ananth.narayan@amd.com, santosh.shukla@amd.com
Subject: Re: [PATCH 02/13] perf/x86/amd: Add IBS OP_DATA2/3 register bit definitions
Date: Thu, 26 May 2022 10:08:54 -0500 [thread overview]
Message-ID: <365af18b-552e-bdcc-20ee-c6ce6e172500@amd.com> (raw)
In-Reply-To: <20220525093938.4101-3-ravi.bangoria@amd.com>
On 5/25/22 4:39 AM, Ravi Bangoria wrote:
Hi Ravi,
> AMD IBS OP_DATA2 and OP_DATA3 provides detail about tagged load/store
> ops. Add definitions for these registers into header file. In addition
> to those, IBS_OP_DATA2 DataSrc provides detail about location of the
> data being accessed from by load ops. Define macros for legacy and
> extended DataSrc values.
>
> Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
> ---
> arch/x86/include/asm/amd-ibs.h | 76 ++++++++++++++++++++++++++++++++++
> 1 file changed, 76 insertions(+)
>
> diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h
> index aabdbb5ab920..22184fe20cf0 100644
> --- a/arch/x86/include/asm/amd-ibs.h
> +++ b/arch/x86/include/asm/amd-ibs.h
> @@ -6,6 +6,82 @@
>
> #include <asm/msr-index.h>
>
> +/* IBS_OP_DATA2 Bits */
> +#define IBS_DATA_SRC_HI_SHIFT 6
> +#define IBS_DATA_SRC_HI_MASK (0x3ULL << IBS_DATA_SRC_HI_SHIFT)
Is there a reason we're not using the existing bitfield
definitions? E.g., data_src_hi for the case above.
Thanks,
Kim
next prev parent reply other threads:[~2022-05-26 15:09 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-25 9:39 [PATCH 00/13] perf mem/c2c: Add support for AMD Ravi Bangoria
2022-05-25 9:39 ` [PATCH 01/13] perf/mem: Introduce PERF_MEM_LVLNUM_{EXTN_MEM|IO} Ravi Bangoria
2022-05-25 9:39 ` [PATCH 02/13] perf/x86/amd: Add IBS OP_DATA2/3 register bit definitions Ravi Bangoria
2022-05-26 15:08 ` Kim Phillips [this message]
2022-06-01 4:25 ` Ravi Bangoria
2022-05-25 9:39 ` [PATCH 03/13] perf/x86/amd: Support PERF_SAMPLE_DATA_SRC based on IBS_OP_DATA* Ravi Bangoria
2022-05-25 9:39 ` [PATCH 04/13] perf/x86/amd: Support PERF_SAMPLE_WEIGHT using IBS OP_DATA3[IbsDcMissLat] Ravi Bangoria
2022-05-25 12:58 ` Stephane Eranian
2022-05-26 12:14 ` Ravi Bangoria
2022-05-25 9:39 ` [PATCH 05/13] perf/x86/amd: Support PERF_SAMPLE_ADDR using IBS_DC_LINADDR Ravi Bangoria
2022-05-25 9:39 ` [PATCH 06/13] perf/x86/amd: Support PERF_SAMPLE_PHY_ADDR using IBS_DC_PHYSADDR Ravi Bangoria
2022-05-25 11:21 ` Peter Zijlstra
2022-05-26 8:46 ` Ravi Bangoria
2022-05-26 9:56 ` Peter Zijlstra
2022-05-26 10:59 ` Ravi Bangoria
2022-05-26 11:09 ` Peter Zijlstra
2022-05-25 9:39 ` [PATCH 07/13] perf tool: Sync include/uapi/linux/perf_event.h header Ravi Bangoria
2022-05-25 9:39 ` [PATCH 08/13] perf tool: Sync arch/x86/include/asm/amd-ibs.h header Ravi Bangoria
2022-05-25 9:39 ` [PATCH 09/13] perf mem: Add support for printing PERF_MEM_LVLNUM_{EXTN_MEM|IO} Ravi Bangoria
2022-05-25 9:39 ` [PATCH 10/13] perf mem/c2c: Set PERF_SAMPLE_WEIGHT for LOAD_STORE events Ravi Bangoria
2022-05-25 9:39 ` [PATCH 11/13] perf mem/c2c: Add load store event mappings for AMD Ravi Bangoria
2022-05-25 9:39 ` [PATCH 12/13] perf mem/c2c: Avoid printing empty lines for unsupported events Ravi Bangoria
2022-05-25 9:39 ` [PATCH 13/13] perf mem: Use more generic term for LFB Ravi Bangoria
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