From: Dave Hansen <dave.hansen@intel.com>
To: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Jiri Olsa <jolsa@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Kan Liang <kan.liang@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
broonie@kernel.org, Ravi Bangoria <ravi.bangoria@amd.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Dapeng Mi <dapeng1.mi@intel.com>
Subject: Re: [Patch v4 03/17] x86/fpu/xstate: Add xsaves_nmi
Date: Mon, 29 Sep 2025 12:01:47 -0700 [thread overview]
Message-ID: <3921d500-36ce-409c-8730-6be86a40e334@intel.com> (raw)
In-Reply-To: <8476ee65-546a-47ff-951c-5b2a24995ccf@linux.intel.com>
On 9/27/25 22:31, Mi, Dapeng wrote:
>> Also, what supervisor components are involved here? Aren't we just
>> talking about [XYZ]MM's?
> Besides the SIMD registers [XYZ]MM, the CET_USR (only SSP) and APX eGPRs
> would be supported as well.
We should think long and hard about whether to use XSAVE for the CET
SSP. I'm not convinced it's worth it.
next prev parent reply other threads:[~2025-09-29 19:01 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-25 6:11 [Patch v4 00/17] Support vector and more extended registers in perf Dapeng Mi
2025-09-25 6:11 ` [Patch v4 01/17] perf/x86: Use x86_perf_regs in the x86 nmi handler Dapeng Mi
2025-09-25 6:11 ` [Patch v4 02/17] perf/x86: Setup the regs data Dapeng Mi
2025-09-25 6:11 ` [Patch v4 03/17] x86/fpu/xstate: Add xsaves_nmi Dapeng Mi
2025-09-25 15:07 ` Dave Hansen
2025-09-28 5:31 ` Mi, Dapeng
2025-09-29 19:01 ` Dave Hansen [this message]
2025-09-30 2:44 ` Mi, Dapeng
2025-09-25 6:12 ` [Patch v4 04/17] perf: Move has_extended_regs() to header file Dapeng Mi
2025-09-25 6:12 ` [Patch v4 05/17] perf/x86: Support XMM register for non-PEBS and REGS_USER Dapeng Mi
2025-09-25 6:12 ` [Patch v4 06/17] perf: Support SIMD registers Dapeng Mi
2025-09-25 6:12 ` [Patch v4 07/17] perf/x86: Move XMM to sample_simd_vec_regs Dapeng Mi
2025-09-25 6:12 ` [Patch v4 08/17] perf/x86: Add YMM into sample_simd_vec_regs Dapeng Mi
2025-09-25 6:12 ` [Patch v4 09/17] perf/x86: Add ZMM " Dapeng Mi
2025-09-25 6:12 ` [Patch v4 10/17] perf/x86: Add OPMASK into sample_simd_pred_reg Dapeng Mi
2025-09-25 6:12 ` [Patch v4 11/17] perf/x86: Add eGPRs into sample_regs Dapeng Mi
2025-09-25 6:12 ` [Patch v4 12/17] perf/x86: Add SSP " Dapeng Mi
2025-09-25 6:12 ` [Patch v4 13/17] perf/x86/intel: Enable PERF_PMU_CAP_SIMD_REGS Dapeng Mi
2025-09-25 6:12 ` [Patch v4 14/17] perf tools: Only support legacy regs for the PT and PERF_REGS_MASK Dapeng Mi
2025-09-25 6:12 ` [Patch v4 15/17] perf tools: headers: Sync with the kernel sources Dapeng Mi
2025-09-25 6:12 ` [Patch v4 16/17] perf tools: parse-regs: Support the new SIMD format Dapeng Mi
2025-09-25 6:12 ` [Patch v4 17/17] perf tools: regs: Support to dump regs for PERF_SAMPLE_REGS_ABI_SIMD Dapeng Mi
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