From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: "Liang, Kan" <kan.liang@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Dapeng Mi <dapeng1.mi@intel.com>
Subject: Re: [Patch v3 12/22] perf/x86/intel: Update dyn_constranit base on PEBS event precise level
Date: Thu, 17 Apr 2025 09:15:16 +0800 [thread overview]
Message-ID: <3989d25c-2961-46b4-8f77-3c1eab63866a@linux.intel.com> (raw)
In-Reply-To: <a998c0c3-1ec5-4dbe-95fa-fd37648de96a@linux.intel.com>
On 4/16/2025 9:59 PM, Liang, Kan wrote:
>
> On 2025-04-15 9:46 p.m., Mi, Dapeng wrote:
>> On 4/16/2025 12:31 AM, Liang, Kan wrote:
>>> On 2025-04-15 9:53 a.m., Peter Zijlstra wrote:
>>>> On Tue, Apr 15, 2025 at 11:44:18AM +0000, Dapeng Mi wrote:
>>>>> arch-PEBS provides CPUIDs to enumerate which counters support PEBS
>>>>> sampling and precise distribution PEBS sampling. Thus PEBS constraints
>>>>> should be dynamically configured base on these counter and precise
>>>>> distribution bitmap instead of defining them statically.
>>>>>
>>>>> Update event dyn_constraint base on PEBS event precise level.
>>>> What if any constraints are there on this?
>>> Do you mean the static constraints defined in the
>>> event_constraints/pebs_constraints?
>>>
>>>> CPUID is virt host
>>>> controlled, right, so these could be the most horrible masks ever.
>>>>
>>> Yes, it could be changed by VMM. A sanity check should be required if
>>> abad mask is given.
>> Yes, we need a check to restrict the PEBS counter mask into the valid
>> counter mask, and just realized that we can't use hybrid(event->pmu,
>> intel_ctrl) to check counter mask and need a minor tweak since it includes
>> the GLOBAL_CTRL_EN_PERF_METRICS bit.
>>
>> How about this?
>>
>> if (x86_pmu.arch_pebs) {
>> u64 cntr_mask = hybrid(event->pmu, intel_ctrl) &
>> ~GLOBAL_CTRL_EN_PERF_METRICS;
>> u64 pebs_mask = event->attr.precise_ip >= 3 ?
>> pebs_cap.pdists : pebs_cap.counters;
>> if (pebs_mask != cntr_mask)
>> event->hw.dyn_constraint = pebs_mask & cntr_mask;
>> }
>>
> The mask isn't changed after boot. The sanity check should only be done
> once. I think it can be done in the update_pmu_cap() when perf retrieves
> the value. If a bad mask is detected, the PEBS should be disabled.
Yeah, it makes sense. Would do.
>
> Thanks,
> Kan>
>>>> This can land us in EVENT_CONSTRAINT_OVERLAP territory, no?The dyn_constraint is a supplement of the static constraints. It doesn't
>>> overwrite the static constraints.
>>>
>>> In the intel_get_event_constraints(), perf always gets the static
>>> constraints first. If the dyn_constraint is defined, it gets the common
>>> mask of the static constraints and the dynamic constraints. All
>>> constraint rules will be complied.
>>>
>>> if (event->hw.dyn_constraint != ~0ULL) {
>>> c2 = dyn_constraint(cpuc, c2, idx);
>>> c2->idxmsk64 &= event->hw.dyn_constraint;
>>> c2->weight = hweight64(c2->idxmsk64);
>>> }
>>>
>>> Thanks,
>>> Kan
>>>
>
next prev parent reply other threads:[~2025-04-17 1:15 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-15 11:44 [Patch v3 00/22] Arch-PEBS and PMU supports for Clearwater Forest and Panther Lake Dapeng Mi
2025-04-15 11:44 ` [Patch v3 01/22] perf/x86/intel: Add Panther Lake support Dapeng Mi
2025-04-15 11:44 ` [Patch v3 02/22] perf/x86/intel: Add PMU support for Clearwater Forest Dapeng Mi
2025-04-15 11:44 ` [Patch v3 03/22] perf/x86/intel: Parse CPUID archPerfmonExt leaves for non-hybrid CPUs Dapeng Mi
2025-04-15 11:44 ` [Patch v3 04/22] perf/x86/intel: Decouple BTS initialization from PEBS initialization Dapeng Mi
2025-04-15 11:44 ` [Patch v3 05/22] perf/x86/intel: Rename x86_pmu.pebs to x86_pmu.ds_pebs Dapeng Mi
2025-04-15 11:44 ` [Patch v3 06/22] perf/x86/intel: Introduce pairs of PEBS static calls Dapeng Mi
2025-04-15 11:44 ` [Patch v3 07/22] perf/x86/intel: Initialize architectural PEBS Dapeng Mi
2025-04-15 11:44 ` [Patch v3 08/22] perf/x86/intel/ds: Factor out PEBS record processing code to functions Dapeng Mi
2025-04-15 11:44 ` [Patch v3 09/22] perf/x86/intel/ds: Factor out PEBS group " Dapeng Mi
2025-04-15 11:44 ` [Patch v3 10/22] perf/x86/intel: Process arch-PEBS records or record fragments Dapeng Mi
2025-04-15 13:57 ` Peter Zijlstra
2025-04-15 16:09 ` Liang, Kan
2025-04-15 11:44 ` [Patch v3 11/22] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR Dapeng Mi
2025-04-15 13:45 ` Peter Zijlstra
2025-04-16 0:59 ` Mi, Dapeng
2025-04-15 13:48 ` Peter Zijlstra
2025-04-16 1:03 ` Mi, Dapeng
2025-04-15 11:44 ` [Patch v3 12/22] perf/x86/intel: Update dyn_constranit base on PEBS event precise level Dapeng Mi
2025-04-15 13:53 ` Peter Zijlstra
2025-04-15 16:31 ` Liang, Kan
2025-04-16 1:46 ` Mi, Dapeng
2025-04-16 13:59 ` Liang, Kan
2025-04-17 1:15 ` Mi, Dapeng [this message]
2025-04-16 15:32 ` Peter Zijlstra
2025-04-16 19:45 ` Liang, Kan
2025-04-16 19:56 ` Peter Zijlstra
2025-04-22 22:50 ` Liang, Kan
2025-04-15 11:44 ` [Patch v3 13/22] perf/x86/intel: Setup PEBS data configuration and enable legacy groups Dapeng Mi
2025-04-15 11:44 ` [Patch v3 14/22] perf/x86/intel: Add counter group support for arch-PEBS Dapeng Mi
2025-04-15 11:44 ` [Patch v3 15/22] perf/x86/intel: Support SSP register capturing " Dapeng Mi
2025-04-15 14:07 ` Peter Zijlstra
2025-04-16 5:49 ` Mi, Dapeng
2025-04-15 11:44 ` [Patch v3 16/22] perf/core: Support to capture higher width vector registers Dapeng Mi
2025-04-15 14:36 ` Peter Zijlstra
2025-04-16 6:42 ` Mi, Dapeng
2025-04-16 15:53 ` Peter Zijlstra
2025-04-17 2:00 ` Mi, Dapeng
2025-04-22 3:05 ` Mi, Dapeng
2025-04-15 11:44 ` [Patch v3 17/22] perf/x86/intel: Support arch-PEBS vector registers group capturing Dapeng Mi
2025-04-15 11:44 ` [Patch v3 18/22] perf tools: Support to show SSP register Dapeng Mi
2025-04-15 11:44 ` [Patch v3 19/22] perf tools: Enhance arch__intr/user_reg_mask() helpers Dapeng Mi
2025-04-15 11:44 ` [Patch v3 20/22] perf tools: Enhance sample_regs_user/intr to capture more registers Dapeng Mi
2025-04-15 11:44 ` [Patch v3 21/22] perf tools: Support to capture more vector registers (x86/Intel) Dapeng Mi
2025-04-15 11:44 ` [Patch v3 22/22] perf tools/tests: Add vector registers PEBS sampling test Dapeng Mi
2025-04-15 15:21 ` [Patch v3 00/22] Arch-PEBS and PMU supports for Clearwater Forest and Panther Lake Liang, Kan
2025-04-16 7:42 ` Peter Zijlstra
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