From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 423B069957; Fri, 1 Mar 2024 07:46:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709279181; cv=none; b=IPBPsKPGbF3wgj5my30LexUku6eO14L3kuSz2IAj3wKPEB3KqnVv44qzU+/1zVi/eGp4VQatt2qIWQWxZek2OGV/UnvdzE7HUEl6d+QS7wh9DufUwYlJ7rwZQoUI0YbjR3oc+k/YQQU1FU201i/L2KCkRflENG2Uum7fVpiiV/M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709279181; c=relaxed/simple; bh=6xpLEruE9O8cMi56zeDMuizZxGMSGREaurUK+enHYC4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=stJRkbLh+H5uDzta+nzkpwOJAZ1qfkRDSnVGRAOcnEy1mFOHEG6MlfuyEI2Dc0cS+WeK/+GFi1BzB5xYMAkbyvcfom+QKViAWtbXwpta8Vdgfh7DpO2gjanhPWrlCU/q3ZEXHpZ+UW496kppgVbtl7g7s4uI4CLaPj/NprhpRww= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 99F5C1FB; Thu, 29 Feb 2024 23:46:55 -0800 (PST) Received: from [10.162.42.8] (a077893.blr.arm.com [10.162.42.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BB8EC3F762; Thu, 29 Feb 2024 23:46:12 -0800 (PST) Message-ID: <3c5238e5-bf2b-4e6c-a81a-e7d7bb0d9fb4@arm.com> Date: Fri, 1 Mar 2024 13:16:10 +0530 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V16 2/8] KVM: arm64: Prevent guest accesses into BRBE system registers/instructions Content-Language: en-US To: Mark Rutland , Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, will@kernel.org, catalin.marinas@arm.com, Mark Brown , James Clark , Rob Herring , Marc Zyngier , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , linux-perf-users@vger.kernel.org, Oliver Upton , James Morse , kvmarm@lists.linux.dev References: <20240125094119.2542332-1-anshuman.khandual@arm.com> <20240125094119.2542332-3-anshuman.khandual@arm.com> <62e64ddd-266c-414e-b66a-8ca94f3c2bbf@arm.com> From: Anshuman Khandual In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 2/29/24 18:20, Mark Rutland wrote: > Hi Suzuki, > > On Thu, Feb 29, 2024 at 11:45:08AM +0000, Suzuki K Poulose wrote: >> On 27/02/2024 11:13, Anshuman Khandual wrote: >>> On 2/27/24 15:34, Mark Rutland wrote: >>>> On Fri, Feb 23, 2024 at 12:58:48PM +0530, Anshuman Khandual wrote: >>>>> On 2/21/24 19:31, Mark Rutland wrote: >>>>>> On Thu, Jan 25, 2024 at 03:11:13PM +0530, Anshuman Khandual wrote: >>>>>>> Currently BRBE feature is not supported in a guest environment. This hides >>>>>>> BRBE feature availability via masking ID_AA64DFR0_EL1.BRBE field. >>>>>> >>>>>> Does that means that a guest can currently see BRBE advertised in the >>>>>> ID_AA64DFR0_EL1.BRB field, or is that hidden by the regular cpufeature code >>>>>> today? >>>>> >>>>> IIRC it is hidden, but will have to double check. When experimenting for BRBE >>>>> guest support enablement earlier, following changes were need for the feature >>>>> to be visible in ID_AA64DFR0_EL1. >>>>> >>>>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >>>>> index 646591c67e7a..f258568535a8 100644 >>>>> --- a/arch/arm64/kernel/cpufeature.c >>>>> +++ b/arch/arm64/kernel/cpufeature.c >>>>> @@ -445,6 +445,7 @@ static const struct arm64_ftr_bits ftr_id_mmfr0[] = { >>>>> }; >>>>> static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { >>>>> + S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRBE_SHIFT, 4, ID_AA64DFR0_EL1_BRBE_IMP), >>>>> S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), >>>>> ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), >>>>> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), >>>>> >>>>> Should we add the following entry - explicitly hiding BRBE from the guest >>>>> as a prerequisite patch ? >> >> This has nothing to do with the Guest visibility of the BRBE. This is >> specifically for host "userspace" (via MRS emulation). >> >>>>> >>>>> S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRBE_SHIFT, 4, ID_AA64DFR0_EL1_BRBE_NI) >>>> >>>> Is it visbile currently, or is it hidden currently? >>>> >>>> * If it is visible before this patch, that's a latent bug that we need to go >>>> fix first, and that'll require more coordination. >>>> >>>> * If it is not visible before this patch, there's no problem in the code, but >>>> the commit message needs to explicitly mention that's the case as the commit >>>> message currently implies it is visible by only mentioning hiding it. >>>> >>>> ... so can you please double check as you suggested above? We should be able to >>>> explain why it is or is not visible today. >>> >>> It is currently hidden i.e following code returns 1 in the host >>> but returns 0 inside the guest. >>> >>> aa64dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1); >>> brbe = cpuid_feature_extract_unsigned_field(aa64dfr0, ID_AA64DFR0_EL1_BRBE_SHIFT); >>> >>> Hence - will update the commit message here as suggested. >> >> This is by virtue of the masking we do in the kvm/sysreg.c below. > > Yep, once this patch is applied. > > I think we might have some crossed wires here; I'm only really asking for the > commit message (and title) to be updated and clarified. Understood. > > Ignoring the patchlet above, and just considering the original patch: > > IIUC before the patch is applied, the ID_AA64DFR0_EL1.BRBE field is zero for > the guest because we don't have an arm64_ftr_bits entry for the > ID_AA64DFR0_EL1.BRBE field, and so init_cpu_ftr_reg() will leave that as zero > in arm64_ftr_reg::sys_val, and hence when read_sanitised_id_aa64dfr0_el1() > calls read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1), the BRBE field will be zero. Makes sense, but should not arm64_ftr_reg::sys_val be explicitly set to '0' via ID_AA64DFR0_EL1_BRBE_NI via adding a S_ARM64_FTR_BITS() into ftr_id_aa64dfr0[] ? OR because it's going to be made visible via S_ARM64_FTR_BITS(FTR_VISIBLE , ...., ID_AA64DFR0_EL1_BRBE_IMP) for enabling it in the guest, this might not be necessary for now. Besides it is also being blocked explicitly now via this patch in read_sanitised_id_aa64dfr0_el1(). > > This series as-is doesn't add an arm64_ftr_bits entry for ID_AA64DFR0_EL1.BRBE, > so it'd still be hidden from a guest regardless of whether we add explicit > masking in read_sanitised_id_aa64dfr0_el1(). The reason to add that masking is > to be explicit, so that if/when we add an arm64_ftr_bits entry for > ID_AA64DFR0_EL1.BRBE, it isn't exposed to a guest unexpectedly. > > Similarly, IIUC the BRBE register accesses are *already* trapped, and > emulate_sys_reg() will log a warning an inject an UNDEFINED exception into the > guest if the guest tries to access the BRBE registers. Any well-behaved guest > *shouldn't* do that, but a poorly-behaved guest could do that and (slowly) spam > dmesg with messages about the unhandled sysreg traps. The reasons to handle > thos regs is largely to suppress that warning, and to make it clear that we > intend for those to be handled as undef. Understood. > > So the commit title should be something like: > > KVM: arm64: explicitly handle BRBE register accesses as UNDEFINED > > ... and the message should mention the key points from the above. > > Suzuki, does that sound right to you? > > Anshuman, can you go re-write the commit message with that in mind? Sure, will something like the following be okay ? KVM: arm64: Explicitly handle BRBE register accesses as UNDEFINED Although ID_AA64DFR0_EL1.BRBE field is zero for the guest because there is no arm64_ftr_bits[] entry for the ID_AA64DFR0_EL1.BRBE field while getting processed for read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1), this masks BRBE feature here to be rather explicit. This will prevent unexpected exposure of BRBE feature to guest when arm64_ftr_bits[] changes for ID_AA64DFR0_EL1. This also makes all guest accesses into BRBE registers, and instructions as undefined access explicitly.